MT48H32M16LFCJ-75 Micron Technology Inc, MT48H32M16LFCJ-75 Datasheet - Page 12

• Manufacturer Part Number: MT48H32M16LFCJ-75
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48H32M16LFCJ-75

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 9/6ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 90mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Functional Description
Initialization
Register Definition
Mode Register
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. J 2/08 EN
In general, the 512Mb SDRAMs (4 Meg x 32 x 4 banks) are quad-bank DRAMs that
operate at 1.8V and include a synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK).
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1
select the bank, A0–A12 select the row). The address bits (A0–A9 for x16 and A0–A8 for
x32) registered coincident with the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections
provide detailed information covering device initialization, register definition,
command descriptions, and device operation.
SDRAMs must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operation. Once the
power is applied to V
is defined as a signal cycling within timing constraints specified for the clock ball), the
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND
INHIBIT or NOP . Starting at some point during this 100µs period and continuing at least
through the end of this period, COMMAND INHIBIT or NOP commands should be
applied.
Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command must be applied. All banks
must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO
REFRESH cycles are complete, the SDRAM is ready for programming the mode registers.
Because the mode registers will power up in an unknown state, they should be loaded
prior to applying any operational command.
There are two mode registers in the component: mode register and extended mode
register (EMR). The mode register is illustrated in Figure 6 on page 14. The mode register
is used to define the specific mode of operation of the SDRAM. This definition includes
the selection of a burst length (BL), a burst type, a CAS latency (CL), an operating mode
and a write burst mode, as shown in Figure 6 on page 14. The mode register is
programmed via the LOAD MODE REGISTER command and will retain the stored
information until it is programmed again or the device loses power.
Mode register bits M0–M2 specify the BL, M3 specifies the type of burst, M4–M6 specify
the CL, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and
M10 and M11 should be set to zero. M12 and M13 should be set to zero to prevent the
extended mode register from being programmed.
DD
512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
and V
12
DD
Q (simultaneously) and the clock is stable (stable clock
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Functional Description
©2005 Micron Technology, Inc. All rights reserved.