ICS83905AG IDT, Integrated Device Technology Inc, ICS83905AG Datasheet - Page 6

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ICS83905AG

Manufacturer Part Number
ICS83905AG
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of ICS83905AG

Lead Free Status / Rohs Status
Not Compliant

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ICS83905 Data Sheet
AC Electrical Characteristics
Table 6A. AC Characteristics, V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at ƒ ≤ f
Terminated at 50
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: See phase noise plot.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
Table 6B. AC Characteristics, V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at ƒ ≤ f
Terminated at 50
NOTE 1: XTAL_IN can be overdriven relative to a signal a crystal would provide.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: See phase noise plot.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
ICS83905AM REVISION B JULY 20, 2009
Symbol
f
tsk(o)
tjit(Ø)
t
odc
t
t
Symbol
f
tsk(o)
tjit
t
odc
t
t
MAX
R
EN
DIS
MAX
R
EN
DIS
/ t
/ t
F
F
Parameter
Output Frequency
Output Skew; NOTE 2, 3
RMS Phase Jitter (Random); NOTE 4
Output Rise/Fall Time
Output Duty Cycle
Output Enable
Time; NOTE 5
Output Disable
Time; NOTE 5
Parameter
Output Frequency
Output Skew; NOTE 2, 3
RMS Phase Jitter (Random); NOTE 4
Output Rise/Fall Time
Output Duty Cycle
Output Enable
Time; NOTE 5
Output Disable
Time; NOTE 5
to V
to V
DDO
DDO
/2.
/2.
MAX
MAX
Using External Crystal
Using External Clock
Source NOTE 1
ENABLE1
ENABLE2
ENABLE1
ENABLE2
Using External Crystal
Using External Clock
Source NOTE 1
ENABLE1
ENABLE2
ENABLE1
ENABLE2
using a crystal input unless noted otherwise.
using a crystal input unless noted otherwise.
DD
DD
= V
= V
DDO
DDO
= 3.3V ± 5%,T
= 2.5V ± 5%,T
25MHz, Integration Range:
25MHz, Integration Range:
A
A
Test Conditions
Test Conditions
100Hz – 1MHz
= 0°C to 70°C
= 0°C to 70°C
100Hz – 1MHz
20% to 80%
20% to 80%
6
LOW SKEW, 1:6 CRYSTAL-TO-LVCMOS/LVTTL FANOUT BUFFER
Minimum
Minimum
200
200
DC
DC
10
48
10
47
Typical
Typical
0.13
0.26
©2009 Integrated Device Technology, Inc.
DDO
DDO
Maximum
Maximum
100
800
/2.
/2.
100
800
40
80
52
40
80
53
4
4
4
4
4
4
4
4
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
Units
Units
MHz
MHz
MHz
MHz
ps
ps
ps
%
ps
ps
ps
%

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