TS68EN360MAB/Q33L E2V, TS68EN360MAB/Q33L Datasheet - Page 8

• Manufacturer Part Number: TS68EN360MAB/Q33L
• Manufacturer: E2V

Specifications of TS68EN360MAB/Q33L

• Operating Temperature (max): 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 1. System Bus Signal Index (Normal Operation) (Continued)
Note:
8
Clock and Test
Clock and Test
(Cont’d)
Power
--
Group
1. I denotes input, O denotes output and I/O is input/output.
0886C–HIREL–04/08
Signal Name
System Clock Out 1
System Clock Out 2
Crystal Oscillator
External Filter Capacitor
Clock Mode Select 1-0
Instruction Fetch/
Development Serial Input
Instruction Pipe 0/
Development Serial
Output
Instruction Pipe 1/Row
Address Select 1
Double-Drive
Breakpoint/Development
Serial Clock
Freeze/Initial
Configuration 2
Three-State
Test Clock
Test Mode Select
Test Data In
Test Data Out
Test Reset
Clock Synthesizer Power
Clock Synthesizer
Ground
Clock Out Power
Clock Out Ground
Special Ground 1
Special Ground 2
System Power Supply
and Return
No Connect
MODCK1-MODCK0
FREEZE/CONFIG2
IPIPE1/RAS1DD
BKPT/DSCLK
EXTAL, XTAL
IFETCH/DSI
IPIPE0/DSO
Mnemonic
VCC, GND
NC4-NC1
VCCSYN
GNDSYN
GNDCLK
VCCCLK
GNDS1
GNDS2
CLKO1
CLKO2
TRST
TRIS
TMS
TDO
XFC
TCK
TDI
Controls test mode operations. (I)
Ground supply to the PLL of the clock synthesizer
Function
Internal system clock output 1. (O)
Internal system clock output 2 - normally 2x CLKO1. (O)
Connections for an external crystal to the internal oscillator
circuit. EXTAL (I), XTAL (O)
Connection pin for an external capacitor to filter the circuit of
the PLL. (I)
Selects the source of the internal system clock. (I) THESE
PINS SHOULD NOT BE SET TO 00
Indicates when the CPU32+ is performing an instruction word
prefetch (O) or input to the CPU32+ background debug mode.
(I)
Used to track movement of words through the instruction
pipeline (O) or output from the CPU32+ background debug
mode. (O)
Used to track movement of words through the instruction
pipeline (O), or a row address select 1 “double-drive” output
(O)
Signals a hardware breakpoint to the QUICC (open-drain I/O),
or clock signal for CPU32+ background debug mode (I)
Indicates that the CPU32+ has acknowledged a breakpoint
(O), or initial QUICC configuration select (I)
Used to three-state all pins if QUICC is configured as a
master. Always Sampled except during system reset. (I)
Provides a clock for Scan test logic. (I)
Serial test instructions and test data signal. (I)
Serial test instructions and test data signal. (O)
Provides an asynchronous reset to the test controller. (I)
Power supply to the PLL of the clock synthesizer
Power supply to clock out pins
Ground supply to clock out pins
Special ground for fast AC timing on certain system bus
signals
Special ground for fast AC timing on certain system bus
signals
Power supply and return to the QUICC
Four no-connect pins
e2v semiconductors SAS 2008
TS68EN360