MT41J256M8DA-125:H Micron Technology Inc, MT41J256M8DA-125:H Datasheet - Page 112

• Manufacturer Part Number: MT41J256M8DA-125:H
• Manufacturer: Micron Technology Inc

Specifications of MT41J256M8DA-125:H

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Commands – Truth Tables
Table 69: Truth Table – Command
Notes 1–5 apply to the entire table
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
Function
MODE REGISTER SET
REFRESH
Self refresh entry
Self refresh exit
Single-bank PRECHARGE
PRECHARGE all banks
Bank ACTIVATE
WRITE
WRITE
with auto
precharge
READ
READ
with auto
precharge
NO OPERATION
Device DESELECTED
Power-down entry
Power-down exit
ZQ CALIBRATION LONG
ZQ CALIBRATION SHORT
BL8MRS,
BC4MRS
BC4OTF
BL8OTF
BL8MRS,
BC4MRS
BC4OTF
BL8OTF
BL8MRS,
BC4MRS
BC4OTF
BL8OTF
BL8MRS,
BC4MRS
BC4OTF
BL8OTF
Notes:
Symbol
WRAPS4
WRAPS8
RDAPS4
RDAPS8
WRAP
WRS4
WRS8
RDAP
PREA
ZQCL
ZQCS
RDS4
RDS8
MRS
NOP
PDX
ACT
PDE
SRX
PRE
DES
REF
SRE
WR
RD
1. Commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of
the clock. The MSB of BA, RA, and CA are device-, density-, and configuration-dependent.
Cycle
Prev.
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
CKE
Cycle
Next
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
CS# RAS# CAS# WE#
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
112
V
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
H
V
H
V
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
V
X
V
V
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Micron Technology, Inc. reserves the right to change products or specifications without notice.
H
H
H
H
H
H
H
H
H
H
H
H
H
V
X
V
V
L
L
L
L
L
L
L
L
L
L
L
2Gb: x4, x8, x16 DDR3 SDRAM
[2:0]
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
BA
V
V
V
V
V
X
V
V
X
X
Commands – Truth Tables
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
An
V
V
V
V
V
X
V
V
X
X
Row address (RA)
A12
© 2006 Micron Technology, Inc. All rights reserved.
V
V
V
V
V
V
H
V
H
V
H
V
H
V
X
V
V
X
X
L
L
L
L
OP code
A10
H
H
H
H
H
H
H
H
V
V
V
V
X
V
V
L
L
L
L
L
L
L
L
A[11,
9:0]
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
CA
V
V
V
V
V
V
X
V
V
X
X
Notes
6, 11
6, 7
10
12
6
8
8
8
8
8
8
8
8
8
8
8
8
9
6