ED DDR3 1G PCH9000 Samsung Semiconductor, ED DDR3 1G PCH9000 Datasheet - Page 51

• Manufacturer Part Number: ED DDR3 1G PCH9000
• Manufacturer: Samsung Semiconductor
• Type: DDR3 SDRAMr

Specifications of ED DDR3 1G PCH9000

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Access Time (max): 20ns
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 160mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

K4B1G04(08/16)46E
14.3 Address/Command Setup, Hold and Derating :
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value (see Table
48) to the ∆tIS and ∆tIH derating value (see Table 49) respectively.
Example: tIS (total setup time) = tIS(base) + ∆tIS Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
V
the slew rate between the last crossing of V
line between shaded ’V
rate line anywhere between shaded ’V
ating value (see Figure 25).
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of V
Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V
the actual signal is always later than the nominal slew rate line between shaded ’dc to V
Figure 24). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to V
to the actual signal from the dc level to V
For a valid transition the input signal has to remain above/below V
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached V
transition) a valid input signal is still required to complete the transition and reach V
For slew rates in between the values listed in Table 51, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
[ Table 48 ] ADD/CMD Setup and Hold Base-Values for 1V/ns
Note : AC/DC referenced for 1V/ns DQ-slew rate and 2V/ns DQS slew rate
Note : The tIS(base)-AC150 specifications are further adjusted to add an additional 100ps of derating to accommodate for the lower alternate thresh-old
[ Table 49 ] Derating values DDR3-800/1066/1333/1600 tIS/tIH-AC/DC based
CMD/
REF
ADD
Slew
V/ns
rate
(DC) and the first crossing of V
tIS(base)-AC150
of 150mV and another 25ps to account for the earlier reference point [(175mv-150mV)/1 V/ns].
tIH(base)
tIS(base)
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
[ps]
∆tIS
-17
-35
-62
-11
88
59
-2
-6
0
4.0 V/ns
REF
(DC) to ac region’, use nominal slew rate for derating value (see Figure 23). If the actual signal is later than the nominal slew
∆tIH
-10
-16
-26
-40
-60
50
34
-4
0
AC175 Threshold -> V
DDR3-800
200 + 150
IH
∆tIS
-11
-17
-35
-62
88
59
-2
-6
0
(AC)min. Setup (tIS) nominal slew rate for a falling signal is defined as
REF
3.0 V/ns
200
275
REF
(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for der-
REF
(DC) level is used for derating value (see Figure 26).
∆tIH
-10
-16
-26
-40
-60
50
34
-4
0
(DC) and the first crossing of V
∆tIS
-17
-35
-62
-11
88
59
-2
-6
0
2.0 V/ns
∆tIS, ∆tIH Derating [ps] AC/DC based
IH
DDR3-1066
125 + 150
(AC) = V
∆tIH
-10
-16
-26
-40
-60
50
34
125
200
-4
0
IH/IL
Page 51 of 61
CLK,CLK Differential Slew Rate
REF
(AC) for some time tVAC (see Table 50).
∆tIS
-27
-54
96
67
-9
-3
8
6
2
1.8 V/ns
(DC) + 175mV, V
IL
∆tIH
-18
-32
-52
58
42
-2
-8
(AC)max. If the actual signal is always earlier than the nominal slew rate
8
4
IH/IL
DDR3-1333
65+125
(AC).
∆tIS
140
104
-19
-46
65
75
16
14
10
-1
5
1.6 V/ns
REF
IL
(AC) = V
(DC) region’, use nominal slew rate for derating value (see
∆tIH
-10
-24
-44
66
50
16
12
6
0
REF
(DC) - 175mV
∆tIS
112
-38
IH
-11
83
24
20
13
13
7
IL
REF
(DC)min and the first crossing of V
1.4V/ns
(DC)max and the first crossing of V
DDR3-1600
(DC) region’, the slew rate of a tangent line
45+125
120
1Gb DDR3 SDRAM
45
∆tIH
-16
-36
74
58
24
20
14
-2
8
IH/IL
Rev. 1.0 February 2009
(AC) at the time of the rising clock
∆tIS
120
-30
91
32
30
26
21
15
-2
1.2V/ns
∆tIH
-26
84
68
34
30
24
18
-6
8
reference
V
V
V
IH/L(DC)
IH/L(AC)
IH/L(AC)
∆tIS
128
-22
99
40
38
34
29
23
5
1.0V/ns
REF
REF
(DC). If
∆tIH
100
(DC).
-10
84
50
46
40
34
24
10