ED DDR3 1G PCH9000 Samsung Semiconductor, ED DDR3 1G PCH9000 Datasheet - Page 46

• Manufacturer Part Number: ED DDR3 1G PCH9000
• Manufacturer: Samsung Semiconductor
• Type: DDR3 SDRAMr

Specifications of ED DDR3 1G PCH9000

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Access Time (max): 20ns
• Maximum Clock Rate: 1.333GHz
• Operating Supply Voltage (typ): 1.5V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Supply Current: 160mA
• Pin Count: 96
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

K4B1G04(08/16)46E
14.0 Timing Parameters by Speed Grade
[ Table 47 ] Timing Parameters by Speed Bin
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
Average Clock Period
Clock Period
Average high pulse width
Average low pulse width
Clock Period Jitter
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
Cycle to Cycle Period Jitter during DLL locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
Cumulative error across n = 13, 14 ... 49, 50 cycles
Absolute clock HIGH pulse width
Absolute clock Low pulse width
Data Timing
DQS,DQS to DQ skew, per group, per access
DQ output hold time from DQS, DQS
DQ low-impedance time from CK, CK
DQ high-impedance time from CK, CK
Data setup time to DQS, DQS referenced to
V
Data hold time to DQS, DQS referenced to
V
DQ and DM Input pulse width for each input
Data Strobe Timing
DQS, DQS READ Preamble
DQS, DQS differential READ Postamble
DQS, DQS output high time
DQS, DQS output low time
DQS, DQS WRITE Preamble
DQS, DQS WRITE Postamble
DQS, DQS rising edge output access time from rising
CK, CK
DQS, DQS low-impedance time (Referenced from RL-1)
DQS, DQS high-impedance time (Referenced from
RL+BL/2)
DQS, DQS differential input low pulse width
DQS, DQS differential input high pulse width
DQS, DQS rising edge to CK, CK rising edge
DQS,DQS falling edge setup time to CK, CK rising edge
DQS,DQS falling edge hold time to CK, CK rising edge
IH
IH
(AC)V
(AC)V
IL
IL
(AC) levels
(AC) levels
Parameter
Speed
tCK(DLL_OF
tERR(10per)
tERR(11per)
tERR(12per)
tJIT(per, lck)
tJIT(cc, lck)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(nper)
tDS(base)
tDH(base)
tHZ(DQS)
tLZ(DQS)
tCH(avg)
tCH(abs)
tCK(avg)
tCK(abs)
tCL(avg)
tJIT(per)
tCL(abs)
tHZ(DQ)
tDQSCK
Symbol
tLZ(DQ)
tJIT(cc)
tDQSQ
tWPRE
tWPST
tDQSH
tRPRE
tRPST
tDQSL
tDQSS
tDIPW
tQSH
tDSS
tDSH
tQSL
tQH
F)
tCK(avg)min +
tJIT(per)min
- 147
- 175
- 194
- 209
- 222
- 232
- 241
- 249
- 257
- 263
- 269
-0.25
0.47
0.47
-100
0.43
0.43
0.38
-800
0.38
0.38
-400
-800
0.45
0.45
MIN
150
600
-90
0.9
0.3
0.9
0.3
0.2
0.2
75
8
-
-
-
DDR3-800
200
180
tCK(avg)max +
tJIT(per)max
Page 46 of 61
Note 19
Note 11
MAX
0.53
0.53
0.55
0.55
0.25
100
147
175
194
209
222
232
241
249
257
263
269
200
400
400
400
400
400
90
-
-
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)min +
tJIT(per)min
- 132
- 157
- 175
- 188
- 200
- 209
- 217
- 224
- 231
- 237
- 242
tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max
-0.25
-600
-300
-600
MIN
0.47
0.47
0.43
0.43
0.38
0.38
0.38
0.45
0.45
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
100
490
-90
-80
0.9
0.3
0.9
0.3
0.2
0.2
25
8
-
-
-
DDR3-1066
180
160
tCK(avg)max +
tJIT(per)max
See Speed Bins Table
Note 19
Note 11
MAX
0.53
0.53
0.55
0.55
0.25
132
157
175
188
200
209
217
224
231
237
242
150
300
300
300
300
300
90
80
-
-
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)min +
tJIT(per)min
- 118
- 140
- 155
- 168
- 177
- 186
- 193
- 200
- 205
- 210
- 215
-0.25
MIN
0.47
0.47
0.43
0.43
0.38
-500
-255
-500
0.45
0.45
400
-80
-70
0.9
0.3
0.4
0.4
0.9
0.3
0.2
0.2
30
65
8
-
-
-
DDR3-1333
160
140
tCK(avg)max +
tJIT(per)max
Note 19
Note 11
MAX
0.53
0.53
0.55
0.55
0.25
118
140
155
168
177
186
193
200
205
210
215
125
250
250
255
250
250
80
70
-
-
-
-
-
-
-
-
-
-
-
-
-
1Gb DDR3 SDRAM
Rev. 1.0 February 2009
tCK(avg)min +
tJIT(per)min
-0.27
0.47
0.47
-103
-122
-136
-147
-155
-163
-169
-175
-180
-184
-188
0.43
0.43
0.38
-450
-225
-450
0.45
0.45
0.18
0.18
MIN
360
-70
-60
0.9
0.3
0.4
0.4
0.9
0.3
10
45
8
-
-
-
DDR3-1600
140
120
tCK(avg)max +
tJIT(per)max
Note 19
Note 11
MAX
0.53
0.53
0.55
0.55
0.27
103
122
136
147
155
163
169
175
180
184
188
100
225
225
225
225
225
70
60
-
-
-
-
-
-
-
-
-
-
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
Units
tCK
tCK
tCK
tCK
tCK
tCK
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
13, 19, g
11, 13, b
12,13,14
13,14, f
13,14, f
13,14,f
29, 31
30, 31
Note
13, g
d, 17
d, 17
13, g
13, g
c, 32
c, 32
13,f
24
25
26
13
28
6
c