ICS8535AG-01 IDT, Integrated Device Technology Inc, ICS8535AG-01 Datasheet - Page 8

• Manufacturer Part Number: ICS8535AG-01
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of ICS8535AG-01

• Number Of Clock Inputs: 2
• Mode Of Operation: Single-Ended
• Output Frequency: 266MHz
• Output Logic Level: LVPECL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Signal Type: LVCMOS/LVTTL
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / Rohs Status: Not Compliant

R
I
CLK I
For applications not requiring the use of a clock input, it can be
left floating. Though not required, but for additional protection, a
1k
LVCMOS C
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
T
IDT
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
NPUTS
RTT =
ERMINATION FOR
ECOMMENDATIONS FOR
ICS8535-01
LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
™
resistor can be tied from the CLK input to ground.
/ ICS
NPUT
((V
:
F
™
FOUT
OH
IGURE
:
3.3V LVPECL FANOUT BUFFER
ONTROL
+ V
OL
2A. LVPECL O
) / (V
1
resistor can be used.
P
INS
LVPECL O
CC
Z
Z
:
– 2)) – 2
o
o
= 50
= 50
U
NUSED
Z
o
50
UTPUT
UTPUTS
I
NPUT AND
T
RTT
ERMINATION
50
A
V
PPLICATION
CC
FIN
- 2V
O
UTPUT
P
INS
8
I
NFORMATION
O
LVPECL O
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal dis-
tortion. Figures 2A and 2B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts
may exist and it would be recommended that the board design-
ers simulate to guarantee compatibility across all printed circuit
and clock component process variations.
UTPUTS
FOUT
F
IGURE
:
UTPUT
2B. LVPECL O
Z
Z
o
o
= 50
= 50
ICS8535AG-01 REV. F OCTOBER 27, 2008
125
84
UTPUT
3.3V
125
84
T
ERMINATION
FIN