GWIXP465BAB Intel, GWIXP465BAB Datasheet - Page 61
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GWIXP465BAB
Manufacturer Part Number
GWIXP465BAB
Description
Manufacturer
Intel
Datasheet
1.GWIXP465BAB.pdf
(163 pages)
Specifications of GWIXP465BAB
Core Operating Frequency
266MHz
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
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Package Information
Table 15.
May 2005
61
UTP_OP_DATA[7] /
SMII_TXDATA[4]
UTP_OP_ADDR[4:0]
UTP_OP_FCI
NOTE: This table discusses all features supported on the Intel
† For a legend of the Type codes, see
†† For information on selecting the desired interface, see the Intel
Name
see
Table 1 on page
UTOPIA Level 2/MII_A/ SMII[4] Interface (Sheet 3 of 9)
Power
Reset
on
Z
Z
Z
14.
†
Reset
VI
Z
Z
Table 10 on page
†
Software
Enables
Normal
Reset
After
Until
VI
Z
Z
46.
Software
Enables
Normal
After
VO
VO
®
VI
IXP45X and Intel
®
IXP45X and Intel
Type
TRI
O
I
†
UTOPIA Mode of Operation:
UTOPIA output data. Also known as UTP_TX_DATA. Used to send data from the
an ATM UTOPIA Level 2-compliant PHY.
MII Mode of Operation:
Not used.
SMII mode of operation:
Output data for SMII interface number four. The data on this signal is transmitted synchronously
with respect to the rising edge of SMII_CLK when operating as an SMII interface and
synchronously with respect to the rising edge of SMII_TXCLK when operating as a Source
Synchronous SMII interface
Transmit PHY address bus. Used by the processor when operating in MPHY mode to poll and
select a single PHY at any given time.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the UTOPIA
and/or the NPE-A Ethernet soft fuse (refer to Expansion Bus Controller chapter of the Intel
IXP45X and Intel
being used in a system design, this interface/signal is not required for any connection.
UTOPIA Output data flow control input: Also known as the TXFULL/CLAV signal.
Used to inform the processor of the ability of each polled PHY to receive a complete cell. For cell-
level flow control in an MPHY environment, TxClav is an active high tri-stateable signal from the
MPHY to ATM layer. The UTP_OP_FCI, which is connected to multiple MPHY devices, will see
logic high generated by the PHY, one clock after the given PHY address is asserted — when a full
cell can be received by the PHY. The UTP_OP_FCI will see a logic low generated by the PHY one
clock cycle, after the PHY address is asserted — if a full cell cannot be received by the PHY.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-KΩ resistor. When this interface is disabled via the UTOPIA
and/or the NPE-A Ethernet soft fuse (refer to Expansion Bus Controller chapter of the Intel
IXP45X and Intel
being used in a system design, this interface/signal is not required for any connection.
®
IXP46X Product Line of Network Processors. For details on feature support listed by processor,
®
IXP46X Product Line of Network Processors Developer’s Manual.
®
®
Intel
IXP46X Product Line of Network Processors Developer’s Manual) and is not
IXP46X Product Line of Network Processors Developer’s Manual) and is not
®
IXP45X and Intel
®
Description
IXP46X Product Line of Network Processors Datasheet
Document Number:
processor
306261-002
®
®
to
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