GWIXP465BAB Intel, GWIXP465BAB Datasheet - Page 155
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GWIXP465BAB
Manufacturer Part Number
GWIXP465BAB
Description
Manufacturer
Intel
Datasheet
1.GWIXP465BAB.pdf
(163 pages)
Specifications of GWIXP465BAB
Core Operating Frequency
266MHz
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
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5.6.2.7.3
Figure 42.
Intel
Document Number:
®
IXP45X and Intel
NOTE: Notice that the access is an Intel-style simplex read access. The data strobe phase is set to a value to last
EX_IOWAIT_N
EX_IOWAIT_N
The EX_IOWAIT_N signal is available to be shared by devices attached to chip selects 0 through
7, when configured in Intel or Motorola modes of operation. The shared device will assert
EX_IOWAIT_N in the T2 phase or a read or write transaction. During idle cycles, the board is
responsible for ensuring that EX_IOWAIT_N is pulled-up. The Expansion bus controller will
always ignore EX_IOWAIT_N for Synchronous Intel mode writes.
When an external device asserts EX_IOWAIT_N before the first cycle of a Strobe phase of a read
or write transaction, the Expansion bus controller will hold in the Strobe phase until the
EX_IOWAIT_N signal returns to an inactive state. Since there is a synchronizer cell on
EX_IOWAIT_N, the external device must assert EX_IOWAIT_N three cycles before the
deassertion of EX_WR_N/EX_RD_N. This implies that the value programmed in the T2 and T3
phase cannot both be equal to zero. After EX_IOWAIT_N is deasserted the Expansion bus
controller will transition to the T4 - Hold state after the T3 counter reaches zero.
The EX_IOWAIT_N signal only affects the interface during the strobe phase of a read/write
transfer. If Chip Selects 4 through 7 are configured in HPI mode of operation, each chip select will
have a corresponding HRDY signal called EX_RDY. The polarity of the ready signal is
programmable. Chip Select 4 corresponds to EX_RDY signal 0 and Chip Select 7 corresponds to
EX_RDY signal 3.
Expansion Bus I/O Wait
EX_ADDR
EX_RD_N
EX_CS_N
EX_DATA
306261-002
three clock cycles. The data is returned from the peripheral device prior to the three clocks and the
peripheral device de-asserts EX_IOWAIT_N. The data strobe phase terminates after two clocks even though
the strobe phase was configured to pulse for three clocks.
EX_CLK
®
IXP46X Product Line of Network Processors Datasheet
(1 Cycle)
T1
(1 Cycle)
T2
Valid Address
(3 Cycles)
T3
Valid Data
Electrical Specifications
(1 Cycle)
T4
(1 Cycle)
T5
A9589-01
May 2005
155
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