PEB20571FV31XT Infineon Technologies, PEB20571FV31XT Datasheet - Page 144

• Manufacturer Part Number: PEB20571FV31XT
• Manufacturer: Infineon Technologies

Specifications of PEB20571FV31XT

• Lead Free Status / Rohs Status: Compliant

Table 42
Interrupt
INT0
INT1
INT2
NMI
4.8
4.8.1
The DSP Control Unit (DCU) controls the DSP access to DELIC’s blocks. It performs the
following tasks:
• DSP program and data address decoding
• Interrupt handling
• Data Bus and Program Bus arbitration
• DSP run time statistics
• Boot support
• Emulation support
4.8.2
The DCU decodes the DSP data address bus (DXAP) and the DSP program address
bus (PPAP) for performing the following tasks:
• Generating the DSP memory mapped register controls, based on decoding of the
• Generating the GHDLC, TRANSIU, HDLCU, IOMU and PCMU RAM controls
• Generating program and data RAM controls upon detection of their address
• Generating the read signal for the program ROM
4.8.3
The following events are reported by the various telecom peripheral blocks to the DSP:
• GHDLC
• DMA mailbox
• µP mailbox
• IOM interface Frame synchronization (FSC) interrupt
• PCM interface Frame synchronization (PFS) interrupt
The GHDLC, DMA Mailbox and Microprocessor Mailbox interrupt sources are assigned
to the DSP interrupts (INT0, INT1 and INT2) as shown in
are reported as status bits (require DSP polling) in the Status Event Register (STEVE).
Data Sheet
8 MSB lines of the data address bus
DSP Control Unit
General
DSP Address Decoding
Interrupt Handling
Interrupt Map
Source
µP DMA Mailbox
µP General Mailbox
FSC & PFS
GHDLC
127
Figure
Functional Description
42. The FSC and PFS
PEB 20570
PEB 20571
2003-07-31