PEB20571FV31XT Infineon Technologies, PEB20571FV31XT Datasheet - Page 124
PEB20571FV31XT
Manufacturer Part Number
PEB20571FV31XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEB20571FV31XT.pdf
(308 pages)
Specifications of PEB20571FV31XT
Lead Free Status / Rohs Status
Compliant
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Note: In 1 x 16.384 Mbit/s only the first half of the frame is saved in the buffer.
4.4.1.4
The PCMU may support different serial data rates:
• up to 4 ports with 2048 Mbit/s (32 time slots per frame)
• up to 2 ports with 4.096 Mbit/s (64 time slots per frame)
• 1 port with 8.196 Mbit/s (128 time slots per frame)
• 1 port with 16.384 Mbit/s (only 128 time slots of the frame are supported)
The PCMU circular buffer may handle up to 128 time slots per frame. Thus, when e.g.
configured in 4.096 Mbit/s mode, only PCM port 0 and 2 are used. In this case PCM
port 1 and 3 remain in IDLE mode, i.e. the TXD1, TXD3 output pins are tri-stated.
For the data rate modes up to 8.192 MBit/s, single rate Data Clock (PDC) or double rate
Data Clock may be selected. For 16.384 MHz mode only single clock is supported.
Single Data Rate PDC Mode
• Serial transmission via TXDn with every DCL rising edge
• Sampling of the incoming serial data (RXDn) with every PDC falling edge
• Sampling PFS with every PDC falling edge. Sampling of PFS = 1 after sampling of
Double Data Rate PDC Mode
• Two PDC cycles per bit (the bits are aligned to the frame start)
• Serial transmission via TXDn with every second PDC rising edge.
• Sampling of incoming serial data (RXDn) with the second PDC falling edge of each bit.
• Sampling of PFS every PDC falling edge. Sampling of PFS = 1 after sampling of
Data Sheet
Table 36
Data Rate
related port
4 x 2.048 Mbit/s
2 x 4.096 Mbit/s
1 x 8.192 Mbit/s
1 x 16.384 Mbit/s A080
PFS = 0 is considered to be the start of a frame.
PFS = 0, is considered to be the start of a new frame.
PCMU Interface Data Rate Modes
DSP Access to D-Buffer Output Blocks
A080
A080
A080
A0BF
TXD0
H
H
H
out0
- A0FF
- A0FF
- A09F
H
H
-
H
H
H
A0A0
A0BF
TXD1
Output Buffer Blocks
out1
107
-
-
-
H
H
-
A0C0H -
A0C0
A0DF
A0FFH
TXD2
out2
-
-
H
Functional Description
H
-
A0E0
PEB 20570
PEB 20571
TXD3
H
out3
2003-07-31
- A0FF
-
-
-
H
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