PEB20571FV31XT Lantiq, PEB20571FV31XT Datasheet - Page 284

• Manufacturer Part Number: PEB20571FV31XT
• Manufacturer: Lantiq

Specifications of PEB20571FV31XT

• Lead Free Status / Rohs Status: Compliant

4)
Figure 76
Figure 77
Data Sheet
PDC
PFS
PFS
In PCM Master mode (PFS and PDC are in output mode) PFS rises with a rising edge of PDC, and it’s designed
to be sampled with the falling edge of PDC at any (slave) chip connected to the PCM interface. The first PDC
cycle in which PFS is sampled as logic-1 after a sampling of logic-0, is considered as the first cycle of the new
PCM frame.
PDC
PFS
(8 KHz)
(4 KHz)
(8 KHz)
PFS Timing in Slave Mode (Input PCM Clocks)
PFS Timing in Master Mode
t
PPR
t
PDP
t
PPW
t
t
Electrical Characteristics and Timing Diagrams
PSP
HPR
t
PPW
267
t
HPF
t
PCP
t
PDP
PEB 20570
PEB 20571
2003-07-31