PEB20571FV31XT Lantiq, PEB20571FV31XT Datasheet - Page 274
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PEB20571FV31XT
Manufacturer Part Number
PEB20571FV31XT
Description
Manufacturer
Lantiq
Datasheet
1.PEB20571FV31XT.pdf
(308 pages)
Specifications of PEB20571FV31XT
Lead Free Status / Rohs Status
Compliant
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Figure 64
8.6.2.2
In this mode driving RD ‘low’ causes Read access, driving WR ‘low’ causes Write
access.
In order to work on demultiplexed bus ALE has to be driven ‘high’ all the time.
Table 69
Parameter
A-bus setup time before WR rising
edge
A-bus hold time after WR rising edge t
CS setup time before WR rising edge t
CS hold time after WR rising edge
D-bus setup time before WR rising
edge
D-bus hold time after WR rising edge t
Data Sheet
WR pulse width
A
R/W
DSxCS
D
P Access Timing in Intel/Infineon Mode
Read Cycle Motorola Mode
Timing for Write Cycle in Intel/Infineon Demultiplexed Mode
t
SRWS
Electrical Characteristics and Timing Diagrams
t
t
Symbol
t
t
t
t
DAD
DSD
SAW
HAW
SCW
HCW
SDW
HDW
WW
257
Limit Values
min.
12
5
12
5
6
8
7
max.
t
DSDH
Unit
ns
ns
ns
ns
ns
ns
ns
t
HSRW
Notes
Output load
capacity of
50 pF
PEB 20570
PEB 20571
2003-07-31
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