PEB20571FV31XT Lantiq, PEB20571FV31XT Datasheet - Page 104

• Manufacturer Part Number: PEB20571FV31XT
• Manufacturer: Lantiq

Specifications of PEB20571FV31XT

• Lead Free Status / Rohs Status: Compliant

D-echo Bit Generation in LT-S Mode
In the LT-S mode, the last received D-bit has to be reflected in the next available E-bit
(E=D). If there are no HDLC controllers available, the D-channel is blocked (E=D is
transmitted). Since it is necessary to meet the ITU requirement to react immediately (i.e.,
even when line delays of several bits have occurred) upon the reception of a D-bit by
issuing the E-bit, the E-bit has to be inserted by the VIP. The information about the D-
channel availability is provided to the VIP in the E-bit data field.
Table 28
bit0 (data) bit1(control)
0
1
Information about the availability of HDLC controllers is provided to the IOM-2000 by the
DSP.
Figure 29
Data Sheet
VIP
0
0
D-Echo Bit
D-Echo Bit Generation
D
E
E / D
logic
D
The transmitted E-bit is equal to the received D-bit
The transmitted E-bit is equal to the inverted received D-bit
87
DR
DX
DELIC
Functional Description
E
PEB 20570
PEB 20571
2003-07-31
DSP