PEB20570FV3.1T Infineon Technologies, PEB20570FV3.1T Datasheet - Page 154

• Manufacturer Part Number: PEB20570FV3.1T
• Manufacturer: Infineon Technologies

Specifications of PEB20570FV3.1T

• Lead Free Status / Rohs Status: Not Compliant

2. Select the type of used data bus via DELIC pin "MODE": Intel/ Infineon or Motorola
3. Set byte count by writing the number of bytes to be transferred, minus 1, into
4. Et the end of a transaction, OAK INT0 is automatically activated (if not masked) in
4.10.1.1 Two-cycle DMA Transfer Mode
Depending on the selected bus mode (Intel / Infineon or Motorola), different signals are
used.
In Intel/Infineon mode, the control lines are DACK, RD, WR. Driving RD low when DACK
is low causes a read from the mailbox. Driving WR low when DACK is low causes a write
into the mailbox.
In Motorola mode, the control lines are DACK, R/W, DS. Driving R/W high when DACK
and DS are low causes a read from the mailbox. Driving R/W low when DACK and DS
are low causes a write into the mailbox.
4.10.1.2 Fly-by Mode
In Fly-by mode, the DMA transfer is done in one bus transaction. The DMA controller
controls the DMA mailbox and the conventional memory within the same cycle; write
strobe just when the read data is valid on the bus. See timing diagrams for Intel/Infineon
and for Motorola bus type in
4.10.2
The PEC-mode supports Infineon Ps C16x, which use an integrated Peripherals Event
Controller (PEC) as a DMA controller. This DMA controller is edge sensitive, meaning
edges have to be provided on the DREQ line in order to initiate every DMA transfer.
DREQ is internally controlled by the Read/Write signals. WR falling edge disables
DREQT, i.e. drives it inactive, and RD falling edge does the same for DREQT. Rising
edges of these signals enable DREQs again.
4.10.3
The Transmit DMA mailbox includes:
• A 16-byte FIFO which the DMA controller writes in (addresses TDT0-7) and the OAK
• A 4-bit counter for indicating the number of transfers remaining in the current
Data Sheet
DTXCNT/DRXCNT register (is handled by the OAK firmware).
order to indicate that the mailbox is empty and available for a next operation. The OAK
can mask INT0 as a whole or just one of its components (for receive or transmit
direction) via register DINSTA.
reads out as from 8 regular 16-bit-wide registers.
transaction (register DTXCNT).
PEC Mode.
Transmit DMA Mailbox
Chapter
8.
137
Functional Description
PEB 20570
PEB 20571
2003-07-31