PEF80902HV1.1XT Infineon Technologies, PEF80902HV1.1XT Datasheet - Page 41
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PEF80902HV1.1XT
Manufacturer Part Number
PEF80902HV1.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF80902HV1.1XT.pdf
(83 pages)
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2.4
The S-Transceiver offers the NT state machine described in the User’s Manual V3.4 [8].
The S-transceiver basic configurations are performed via pin strapping.
2.4.1
Line Coding
The following figure illustrates the line code. A binary ONE is represented by no line
signal. Binary ZEROs are coded with alternating positive and negative pulses with two
exceptions:
For the required frame structure a code violation is indicated by two consecutive pulses
of the same polarity. These two pulses can be adjacent or separated by binary ONEs.
In bus configurations a binary ZERO always overwrites a binary ONE.
•
Figure 9
Frame Structure
Each S/T frame consists of 48 bits at a nominal bit rate of 192 kbit/s. For user data
(B1+B2+D) the frame structure applies to a data rate of 144 kbit/s (see
In the direction TE
framing rules please refer to ITU I.430 section 6.3. The following figure illustrates the
standard frame structure for both directions (NT
and maintenance bits.
Data Sheet
S-Transceiver
Line Coding, Frame Structure
S/T -Interface Line Code
NT the frame is transmitted with a two bit offset. For details on the
33
TE and TE
Functional Description
NT) with all framing
0 1 1
Figure
code violation
PEF 80902
2001-11-12
9).
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