5962-8960101B2A QP SEMICONDUCTOR, 5962-8960101B2A Datasheet - Page 21

• Manufacturer Part Number: 5962-8960101B2A
• Manufacturer: QP SEMICONDUCTOR

Specifications of 5962-8960101B2A

• Logic Family: ACT
• Technology: CMOS
• Number Of Bits: 8
• Number Of Elements: 1
• Clock-edge Trigger Type: Positive-Edge
• Polarity: Non-Inverting
• Operating Supply Voltage (typ): 5V
• Propagation Delay Time: 13.5ns
• Output Type: 3-State
• Low Level Output Current: 24mA
• High Level Output Current: -24mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / Rohs Status: Not Compliant

DSCC FORM 2234
APR 97
4.2.2 Additional criteria for device classes B, S, Q, and V.
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.5).
be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for
groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.5).
4.3 Qualification inspection for device classes B, S, Q, and V. Qualification inspection for device classes B, S, Q, and V shall
4.2.3 Percent defective allowable (PDA).
4.4 Conformance inspection. Technology conformance inspection for classes B, S, Q, and V shall be in accordance with
4.4.1 Group A inspection.
b.
c.
a.
a.
b.
c.
d.
e.
a.
b.
c.
b. Latch-up and ground bounce tests are required for device classes B, S, Q, and V. These tests shall be performed only
c.
DEFENSE SUPPLY CENTER COLUMBUS
for initial qualification and after process or design changes which may affect the performance of the device. Latch-up
tests shall be considered destructive. For latch-up and ground bounce tests, test all applicable pins on five devices with
zero failures.
capacitance. C
1 MHz. C
C
Interim and final electrical test parameters shall be as specified in table II herein.
For class S devices, post dynamic burn-in, or class B devices, post static burn-in, electrical parameter measurements
may, at the manufacturer's option, be performed separately or included in the final electrical parameter requirements.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test
method 1015 of MIL-STD-883.
Additional screening for device class V or S beyond the requirements of device class Q or B shall be as specified in
The PDA for class S or V devices shall be 5 percent for static burn-in and 5 percent for dynamic burn-in, based on the
exact number of devices submitted to each separate burn-in.
Static burn-in I and II failures shall be cumulative for determining the PDA.
The PDA for class B or Q devices shall be in accordance with MIL-PRF-38535, for static burn-in. Dynamic burn-in is
not required.
The PDA for class M devices shall be in accordance with MIL-PRF-38535, appendix A for static burn-in and dynamic
burn-in.
Those devices whose measured characteristics, after burn-in, exceed the specified delta limits or electrical parameter
limits specified in table I, subgroup I, are defective and shall be removed from the lot. The verified number of failed
devices times 100 divided by the total number of devices in the lot initially submitted to burn-in shall be used to
determine the percent defective for the lot and the lot shall be accepted or rejected based on the specified PDA.
Tests shall be as specified in table II herein.
C
MIL-PRF-38535, appendix B.
Interim and final electrical test parameters shall be as specified in table II herein.
IN
IN
, C
, C
MICROCIRCUIT DRAWING
COLUMBUS, OHIO 43216-5000
OUT
OUT
, and C
, and C
PD
shall be tested in accordance with the latest revision of JEDEC Standard No. 20 and table I herein. For
STANDARD
IN
PD
PD
and C
, test all applicable pins on five devices with zero failures.
shall be measured only for initial qualification and after process or design changes which may affect
OUT
shall be measured between the designated terminal and GND at a frequency of
SIZE
A
REVISION LEVEL
E
SHEET
5962-89601
21