TS68EN360VA25L E2V, TS68EN360VA25L Datasheet - Page 22

• Manufacturer Part Number: TS68EN360VA25L
• Manufacturer: E2V

Specifications of TS68EN360VA25L

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

Table 7-6.
Notes:
22
Number
80
81
82
83
84
85
86
87
88
89
90
91
92
1. All AC timing is shown with respect to 0.8V and 2.0V levels unless otherwise noted.
2. This number can be reduced to 5 ns if strobes have equal loads.
3. If multiple chip selects are used, the CSx width negated (#15) applies to the time from the negation of a heavily loaded chip
4. Hold times are specified with respect to DS or CSx on asynchronous reads and with respect to CLKO1 on fast termination
5. If the asynchronous setup (#17) requirements are satisfied, the DSACKx low to data setup time (#31) and DSACKx low to
6. To ensure coherency during every operand transfer, BG will not be asserted in response to BR until after cycles of the cur-
7. In the absence of DSACKx, BERR is an asynchronous input using the asynchronous setup time (#47).
8. During interrupt acknowledge cycles, the processor may insert up to two wait states between states S0 and S1.
9. Specs are for Synchronous Arbitration only. ASTM = 1.
10. CSx specs are for TRLX = 0.
11. CSx specs are for TRLX = 1.
12. CSx specs are for CSNTQ = 0.
13. CSx specs are for CSNTQ = 1; or RASx specs for DRAM accesses.
14. Specs are read cycles with parity check and PBEE = 1.
15. Specs are read cycles with parity check and PBEE = 0, PAREN = 1.
16. RASx specs are for page miss case.
17. Specifications only apply to CSx/RASx pins.
18. Specification applies to non fast termination cycles. In fast termination cycles, the BERR signal must be negated by 20 ns
0886C–HIREL–04/08
select to the assertion of a lightly loaded chip select.
reads. The user is free to use either hold time for fast termination reads.
BERR low setup time (#48) can be ignored. The data must only satisfy the data-in to CLKO1 low setup time (#27) for the fol-
lowing clock cycle: BERR must only satisfy the late BERR low to CLKO1 low setup time (#27A) for the following clock cycle.
rent operand transfer are complete and RMC is negated.
after negation of AS, DS.
Characteristic
DSI Input Setup Time
DSI Input Hold Time
DSCLC Setup Time
DSCLC Hold Time
DSO Delay Time
DSCLK Cycle
CLKO1 High to Freeze Asserted
CLKO1 High to Freeze Negated
CLKO1 High to IFETCH High Impedance
CLKO1 High to IFETCH Valid
CLKO1 High to PERR Asserted
CLKO1 High to PERR Negated
V
GND = 0 V
(See
CC
Ramp-Up Time At Power-On Reset
Figure 7-3
DC
, T
C
to
= -55 to +125 C. The electrical specifications in this document are preliminary
Figure
7-19) (Continued)
Symbol
t
t
DSCCYC
t
t
DSCSU
t
t
t
t
t
t
DSISU
t
DSOD
DSCH
FRZN
CHPN
FRZA
CHPA
RMIN
DSIH
t
t
IFZ
IF
Min
10
10
6
6
–
2
0
0
0
0
0
0
5
25 MHz
tcyc+2
Max
35
35
35
35
20
20
–
–
–
–
0
–
–
3.75
3.75
Min
7.5
7.5
–
2
0
0
0
0
0
0
5
33.34 MHz
e2v semiconductors SAS 2008
TS68EN360
tcyc+2
26.25
26.25
26.25
26.25
Max
15
15
–
–
–
–
0
–
–
CLKO1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns