TS68EN360VA25L E2V, TS68EN360VA25L Datasheet
TS68EN360VA25L
Specifications of TS68EN360VA25L
Related parts for TS68EN360VA25L
TS68EN360VA25L Summary of contents
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... SAS 2008 Communication Controller < +125 C C ™ versatile one-chip integrated microprocessor TS68EN360 32-bit Quad Integrated Visit our website: www.e2v.com for the latest version of the datasheet 0886C–HIREL–04/08 ...
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... Screening/Quality This product is manufactured in full compliance with: • QML (class Q) • or according to e2v standards 1. Introduction 1.1 QUICC Architecture Overview The QUICC is 32-bit controller that is an extension of other members of the TS68300 family. Like other members of the TS68300 family, the QUICC incorporates the intermodule bus (IMB). The TS68302 is an exception, having an 68000 bus on chip ...
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... CLKO2 J CLKO1 H D21 G D24 F D27 E D30 D FC2 C SIZ1 B SIZ0 A 1 Note: Pin P9 “NC” is for guide purposes only. e2v semiconductors SAS 2008 PA12 PA9 PA6 PA3 PA2 PB17 PB15 PB12 D0 PA13 PA10 PA7 PA5 PA1 PB16 PB13 D3 D1 PA14 PA11 PA8 ...
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... D31 D30 D29 GND D28 100 D27 D26 Vcc D25 D24 D23 GND D22 D21 D20 90 CLKO1 Vccclk GNDclk CLKO2 D19 D18 D17 GND D16 D15 80 Vcc D14 D13 D12 GND D11 D10 GND D6 D5 Vcc GND e2v semiconductors SAS 2008 ...
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... Signal Description 3.1 Functional Signal Group Figure 3-1. QUICC Functional Signal Groups TIN1/L1RCLKA/BRGO1/CLK1/PA8 TIN2/L1TCLKA/BRGO2/CLK3/PA10 BRGCLK2/L1RCLKB/TOUT3/CLK6/PA13 RRJCT2/SPIMOSI(SPITXD)/PB2 BRGO4/SPIMISO(SPIRXD)/PB3 SDACK2/L1TSYNCB/CTS3/PC8 SDACK1/L1TSYNCA/CTS4/PC10 e2v semiconductors SAS 2008 PORT A RXD1/PA0 TXD1/PA1 RXD2/PA2 TXD2/PA3 L1TXDB/RXD3/PA4 L1RXDB/TXD3/PA5 L1TXDA/RXD4/PA6 L1RXDA/TXD4/PA7 TIMERs/SCCs/SIs/CLOCKs/BRG BRGCLK1/TOUT1/CLK2/PA9 TOUT2/CLK4/PA11 TIN3/BRGO3/CLK5/PA12 TIN4/BRGO4/CLK7/PA14 L1TCLKB/TOUT4/CLK8/PA15 PORT B (PIP) ...
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... Identifies the bus cycle as part of an indivisible RMC read-modify-write operation (I/O) or initial QUICC CONFIG0 configuration select. (I) Indicates that an internal device requires the external bus BCLRO/CONFIG1/ (Open-Drain O) or initial QUICC configuration select (I) or row RAS2DD address select 2 double-drive output. (O) TS68EN360 (1) e2v semiconductors SAS 2008 ...
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... Autovector/Interrupt Acknowledge 5 Soft Reset Hard Reset System Halt Control Bus Error e2v semiconductors SAS 2008 Mnemonic Function Provides asynchronous data transfer acknowledgement and DSACK1 - DSACK0 dynamic bus sizing (open-drain I/O but driven high before three-stated) AS Indicates that a valid address is on the address bus. (I/O) ...
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... Ground supply to clock out pins Special ground for fast AC timing on certain system bus GNDS1 signals Special ground for fast AC timing on certain system bus GNDS2 signals VCC, GND Power supply and return to the QUICC NC4-NC1 Four no-connect pins TS68EN360 e2v semiconductors SAS 2008 ...
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... SPI SPI Clock SPI Select SMC Receive Data SMC SMC Transmit Data SMC Sync e2v semiconductors SAS 2008 Mnemonic Function RXD4-RXD1 Serial receive data input to the SCCs. (I) TXD4-TXD1 Serial transmit data output from the SCCs. (O) Request to send outputs indicate that the SCC is ready to RTS4-RTS1 transmit data ...
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... This input causes the PIP output data to be placed on the STRBO PIP data pins This input causes data on the PIP data pins to be latched by STRBI the PIP as input data SDMA output signals used in RISC receiver to mark fields in SDACK2-SDACK1 the Ethernet receive frame TS68EN360 e2v semiconductors SAS 2008 ...
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... Detailed Specification This specification describes the specific requirements for the microcontroller TS68EN360 - 25 MHz and 33 MHz in compliance with MIL-STD-883 class B or e2v standard screening. 5. Applicable Documents 1. MIL-STD-883: test methods and procedures for electronics 2. MIL-PRF-38535: general specifications for microcircuits 3. DESC 5962-SMD-97607 The microcircuits are in accordance with the applicable document and as specified herein. ...
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... Watts-chip Internal Power CC < 0.3 · P and can be neglected. I/O INT TS68EN360 ) DD Min Typ Max +4.75 +5.25 GND +0.8 +2 -55 +125 +2 Value 240-pin Cerquad 2 241-pin PGA 7 240-pin Cerquad 27.4 241-pin PGA 22.8 (1) e2v semiconductors SAS 2008 Unit MHz MHz Unit C/W C/W ...
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... Equations (1) and (2) iteratively for any value of T 5.4 Mechanical and Environment The microcircuits shall meet all mechanical environmental requirements of either MIL-STD-883 for class B devices or for e2v standard screening. 5.5 Marking The document where are defined the marking are identified in the related reference documents. Each microcircuit are legible and permanently marked with the following information as minimum: • ...
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... The measurement of the AC specifications is defined by the waveforms shown in parameters guaranteed by e2v inputs must be driven to the voltage levels specified in the figure. Outputs are specified with minimum and/or maximum limits, as appropriate, and are measured as shown. Inputs are specified with minimum setup and hold times and are measured as shown. Finally, the measurement for signal-to-signal specifications are shown ...
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... Legend: a) Maximum output delay specification b) Minimum output hold time c) Minimum input setup time specification d) Minimum input hold time specification e) Signal valid to signal valid specification (maximum or minimum) f) Signal valid to signal invalid specification (maximum or minimum) e2v semiconductors SAS 2008 2.0V 0. 2.0V 2.0V VALID ...
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... MHz Divide 6.25 MHz Divide 6.25 MHz Divide 6.25 MHz Divide 390 kHz 0.5 TBD TBD = Unit Mask (1) W REV A and REV B (3) W REV C and Newer (3) W REV C and Newer (3) W REV C and Newer e2v semiconductors SAS 2008 Unit (2) ...
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... MHz ±( 0.25 x (rise time)) (2 rise = 2 ns rise = 4 ns) 5D: 25 MHz ±( 0.5 x (rise time rise = 2 ns rise = 4 ns) 33 MHz ±(2 0.5 x (rise time)) (3 rise = 2 ns; 4 rise = 4 ns) e2v semiconductors SAS 2008 25 MHz Symbol Min Max Min ( ...
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... MF x 380 MF x 970 is: 762 x 380 = 289 nF, XFC for 25 MHz is: 762 x 540 = 414 nF. 289 XFC is 390 nF. XFC is: 1017 x 380 = XFC < 390 nF. The proper available value XFC is: 401 x 970 = 390 nF ⇒ 386 nF < C XFC e2v semiconductors SAS 2008 Unit pF pF < 390 XFC ...
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... CSx Width Asserted (Fast Termination Cycle) (3)(10)(12) 15 AS, DS, CSx, OE, WE Width Negated 16 CLKO1 High to AS, DS, R/W High Impedance (12) 17 AS, DS, CSx, WE Negated to R/W High (13) 17A CSx Negated to R/W High e2v semiconductors SAS 2008 7-19) Symbol t CHAV t CHAV t CHAZx t CHAZn t CLSA ...
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... SAS 2008 Unit CLKO1 CLKO1 CLKO1 ...
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... Data Setup Time to CLKO1 Low (Show Cycle) 72 Data Hold from CLKO1 Low (Show Cycle) 73 BKPT Input Setup Time 74 BKPT Input Hold Time 75 RESETH Low to Config2-0, MOD1-0, B16M Valid 76 Config2-0 77 MOD1-0 Hold Time, B16M Hold Time e2v semiconductors SAS 2008 7-19) (Continued) Symbol RWA t RWAS t AIST t AIHT ...
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... FRZN t IFZ CHPA t CHPN t RMIN TS68EN360 25 MHz 33.34 MHz Min Max Min Max 10 – 7.5 – 6 – 3.75 – 10 – 7.5 – 6 – 3.75 – tcyc+2 tcyc+2 – – – 2 – 26. 26. 26. 26. – 5 – e2v semiconductors SAS 2008 Unit CLKO1 ...
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... Figure 7-3. Read Cycle ASYNCHRONOUS Note: All timing is shown with respect to 0.8V and 2.0V levels. e2v semiconductors SAS 2008 CLKO1 (OUTPUT) 6 A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) RMC (OUTPUT (OUTPUT (OUTPUT) 9A CSx (OUTPUT) OE (OUTPUT R/W (OUTPUT) DSACK0 (I/O) DSACK1 (I/O) 31A ...
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... Fast Termination Read Cycle (Parity Check PAREN = 1, PBEE = 0) (OUTPUT) (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) (OUTPUT) (OUTPUT) (OUTPUT) (OUTPUT) (OUTPUT) D31-D0 (INPUT) (INPUT) (OUTPUT) 24 0886C–HIREL–04/ CLKO1 6 A31-A0 9 14B AS DS CSx OE 18 46A R BKPT PERR TS68EN360 CPU CLEARS PERn BIT 30A e2v semiconductors SAS 2008 ...
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... Figure 7-5. Read Cycle (With Parity Check, PBEE = 1) A31-A0, FC3-FC0, SIZ1-SIZ0 (OUTPUT) ASYNCHRONOUS Note: All timing is shown with respect to 0.8V and 2.0V levels. e2v semiconductors SAS 2008 S0 S1 CLKO1 (OUTPUT) 6 RMC (OUTPUT (OUTPUT (OUTPUT) 9A CSx (OUTPUIT) OE (OUTPUT R/W (OUTPUT) DSACK0 (I/O) ...
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... SRAM: Read Cycle (TRLX = 1) 26 0886C–HIREL–04/ CLKO1 (OUTPUT) 6 A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) RMC (OUTPUT (OUTPUT) 11A DS (OUTPUT) 9B CSx (OUTPUT) 21A OE (OUTPUT) 18 R/W (OUTPUT) DSACK0 (I/O) DSACK1 (I/O) 31A D31-D0 (INPUT) TS68EN360 47A 29 31 29A 27 e2v semiconductors SAS 2008 ...
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... CLKO1 (OUTPUT) A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) AS (OUTPUT) DS (OUTPUT) IACKx (OUTPUT) OE (OUTPUT) 18 R/W (OUTPUT) DSACK0 (I/O) DSACK1 (I/O) D31-D0 (INPUT) Note two wait states may be inserted by the processor between states S0 and S1. e2v semiconductors SAS 2008 * 0-2 CLOCKS TS68EN360 31A 28 47A 31 ...
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... PRTY3-PRTY0 Note: All timing is shown with respect to 0.8V and 2.0V levels. 28 0886C–HIREL–04/ CLKO1 6 A31-A0 FC3-FC0 CSn 22 WEn 20 R/W DSACK0 (I/O) 31A DSACK1 (I/O) 55 D31-D0 23 (OUTPUT) BERR (INPUT) HALT (INPUT) BKPT (INPUT) TS68EN360 14A 47A e2v semiconductors SAS 2008 ...
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... Figure 7-9. Fast Termination Write Cycle Figure 7-10. SRAM: Fast Termination Write Cycle (CSNTQ = 1) e2v semiconductors SAS 2008 CLKO1 (OUTPUT) 6 A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT (OUTPUT) 9 14B CSx (OUTPUT) DS (OUTPUT) WEx (OUTPUT) 20 46A R/W R/W (OUTPUT) 23 D31-D0 (OUTPUT) PRTY3-PRTY0 (OUTPUT) ...
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... BCLRO (OUTPUT) 30 0886C–HIREL–04/ CLKO1 (OUTPUT) A31-A0 (OUTPUT) AS (OUTPUT 11A (OUTPUT) 9B CSx (OUTPUT) WEx (OUTPUT R/W (OUTPUT) DSACK0 (I/O) DSACK1 (I/ D31-D0 (OUTPUT) 23 PRTY0-PRTY3 (OUTPUT) 47A 47A TS68EN360 12A 14C 13A 17A 46 47A 31A 25A 47A 47A e2v semiconductors SAS 2008 ...
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... Figure 7-13. ASYNC Bus Arbitration – Active Bus Case Figure 7-14. SYNC Bus Arbitration – IDLE Bus Case (OUTPUT) A31-A0 (OUTPUT) D31-D0 (OUTPUT) (OUTPUT) (INPUT) (OUTPUT) (OUTPUT) e2v semiconductors SAS 2008 CLKO1 (OUTPUT) A31-A0 (OUTPUT) D31-D0 (OUTPUT) AS (OUTPUT) DS (OUTPUT) R/W (OUTPUT) ...
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... A31-A0 (OUTPUT) D31-D0 (OUTPUT) AS (OUTPUT) DS (OUTPUT) R/W (OUTPUT) DSACK0 (I/O) DSACK1 (I/O) BR (INPUT) BG (OUTPUT) BGACK (INPUT) BCLRO (OUTPUT) Figure 7-16. Configuration and Clock Mode Select Timing RESETH CONFIG2-CONFIG0, MODCK1-MODCK0, 32 0886C–HIREL–04/ 16BM TS68EN360 S98 7 16 39A e2v semiconductors SAS 2008 ...
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... Figure 7-17. Show Cycle Figure 7-18. Background Debug Mode FREEZE Timing Figure 7-19. Background Debug Mode Serial Port Timing e2v semiconductors SAS 2008 S0 S41 S42 CLKO1 (OUTPUT) 6 A31-A0 (OUTPUT) 18 R/W (OUTPUT (OUTPUT (OUTPUT) 70 D31-D0 BKPT (INPUT) SHOW CYCLE CLKO1 86 FREEZE IFETCH/DSI ...
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... D31ÐD0 (INPUT) PARITY3-PARITY0 (INPUT) D31-D0 (INPUT) Note: All timing is shown with respect to 0.8V and 2.0V levels. 34 0886C–HIREL–04/ 108 11 107 12 100 101 102 104 109 110 105 27 PBEE = 0 27B PBEE = 1 TS68EN360 103 106 111 29 e2v semiconductors SAS 2008 SW ...
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... CLKO1 High to AMUX Asserted 121 AMUX High to RASx Asserted 122 RASx Asserted to AMUX Low 123 AMUX Low to CASx Asserted 124 CASx Asserted to AMUX High 125 RAS/CASx Negated to R/W change e2v semiconductors SAS 2008 TS68EN360 25.0 MHz 33.34 MHz Min Max Min Max 15 11.25 20 ...
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... All timing is shown with respect to 0.8V and 2.0V levels. 36 0886C–HIREL–04/ CLKO1 (OUTPUT A31-A0 (OUTPUT (OUTPUT) 9 100 RASx 101 (OUTPUT) CAS3-CAS0 (OUTPUT) 113 WEx (OUTPUT) 20 115 R/W (OUTPUT) DSACK1,0 (I/O) 117 D31-D0 (OUTPUT) 23 (OUTPUT) TS68EN360 108 107 12 102 106 105 110 114 116 17 53 e2v semiconductors SAS 2008 ...
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... Figure 7-23. DRAM: Page Mode – Page-Hit CLKO1 (OUTPUT) A31-A0 (OUTPUT) INTERNAL MUX INTERNAL MUX (OUTPUT) (OUTPUT) CAS3-CAS0 (OUTPUT) AMUX (OUTPUT) Note: All timing is shown with respect to 0.8V and 2.0V levels. e2v semiconductors SAS 2008 S4 S5 105A 12 RASx 12A RASx PAGE MODE NOT IN PAGE MODE ...
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... CLKO1 (OUTPUT) A31-A0 (OUTPUT) INTERNAL MUX AS (OUTPUT) RASn (OUTPUT) CAS3-CAS0 (OUTPUT) AMUX (OUTPUT) Note: All timing is shown with respect to 0.8V and 2.0V levels. 38 0886C–HIREL–04/ 105 122 123 120 EXTERNAL MUX TS68EN360 12A 106 120 119 e2v semiconductors SAS 2008 ...
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... BB (I/O) 60 BCLRO (OUTPUT) BCLRI (INPUT) Notes: 1. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK always remains asserted until either the SDMA or the IDMA requests the external bus e2v semiconductors SAS 2008 25.0 MHz Min 7 – – – – 360 BUS MASTER ...
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... Min Max Min Max 15 – 11.25 – 7 – 6 – 5 – 3 – 0 – 0 – 0 – 0 – 0 – 0 – – 15 – 11.25 – 20 – 15 – 20 – 15 – 15 – – 20 – 15 – 30 – 23 – 30 – 23 – 30 – 23 – 30 – 23 e2v semiconductors SAS 2008 Unit ...
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... RAM and CPM. Four wait states are inserted when writing to the SI RAM. Additional wait states may be inserted when the SHEN1-SHEN0 = 10 and one of the internal masters is accessing an internal peripheral. 2. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK. e2v semiconductors SAS 2008 ...
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... A31-A0 (INPUT) TRANSFER ATTRIBUTES (INPUT) 253 252 TS (INPUT) TA (INPUT) 289 TBI (OUTPUT) 257 AVECO (OUTPUT) 264 IACK7-1 (OUTPUT) 266 TS68EN360 CW CW 254 263 262 260 258 257 259 267 CW CW 254 290 250 265 267 e2v semiconductors SAS 2008 ...
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... CLKO1 High (After TA Low) to Parity Hi-Z Notes: 1. Transfer attributes signals = SIZx, TTx, TMx, R/W and LOCK. 2. TEA/TA should not be asserted on a DRAM burst access the same clock or before RASx/CSx is asserted. 3. The clock reference is EXTAL, not CLK01. e2v semiconductors SAS 2008 Figure 7-34) TS68EN360 25.0 MHz 33 ...
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... BADD3- BADD2 (OUTPUT) 252 TS (INPUT) 282 CSx (OUTPUT) TA (OUTPUT) 257 TBI (OUTPUT) 284 BKPTO (OUTPUT) OE 291 (OUTPUT) (READ CYCLES) 293 WE (OUTPUT) (WRITE CYCLES) TEA (INPUT) TS68EN360 C2 254 281 253 283 258 259 285 292 294 301 300 e2v semiconductors SAS 2008 ...
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... Figure 7-31. TS68040 SRAM Read/Write Cycles (TSS40 = 1, CSNT40 = 1) (OUTPUT) TRANSFER ATTRIBUTES (OUTPUT) (OUTPUT) (OUTPUT) (OUTPUT) (OUTPUT) e2v semiconductors SAS 2008 C1 C2 CLKO1 251 (INPUT) A31-A0 (INPUT) 280 BADD3- BADD2 252 TS (INPUT) CSn 286 TA TBI BKPTO TEA (INPUT) TA (INPUT) TS68EN360 C3 254 281 ...
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... A31-A0 (INPUT) 280 BADD3- BADD2 252 TS (INPUT) RASx CAS3- CAS0 122 121 298 AMUX 297 293 WE TA TBI TEA (INPUT) TS68EN360 C2 C1 281 253 282 283 296 295 123 298 294 258 257 259 300 301 e2v semiconductors SAS 2008 254 ...
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... BADD3- BADD2 (OUTPUT) TS (INPUT) RASx (OUTPUT) CAS3- CAS0 (OUTPUT) AMUX (OUTPUT) WE (WRITE CYCLE OUTPUT) TA (OUTPUT) TBI (OUTPUT) e2v semiconductors SAS 2008 288 253 252 282 295 297 293 257 TS68EN360 C1 C2 299 299 295A 296 296 295 258 257 0886C– ...
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... ATTRIBUTES (INPUT) A31-A0 (INPUT) BADD3- BADD2 (OUTPUT) TS (INPUT) TA (OUTPUT) D31-D0, (INPUT) PRTY3- PRTY0 (INPUT) PERR (OUTPUT) 48 0886C–HIREL–04/08 212 (a) Generation Timing Diagram C1 C2 302 303 305 306 (b) Checking Timing Diagram TS68EN360 213 CPU Clears PERn Bit e2v semiconductors SAS 2008 ...
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... DONE Input Hold Time From CLKO1 Low (2) 16 DREQ Asserted to AS Asserted Notes: 1. These specifications are for asynchronous mode. 2. These specifications are for synchronous mode. e2v semiconductors SAS 2008 Figure 7-36) TS68EN360 25.0 MHz 33.34 MHz Min Max Min Max ...
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... DACK (OUTPUT) DONE (OUTPUT) DONE (INPUT) Figure 7-36. IDMA Signal Synchronous Timing Diagram S0 CLKO1 (OUTPUT) 12 DREQ (INPUT) AS (OUTPUT) DACK (OUTPUT) DONE (OUTPUT) DONE (INPUT) 50 0886C–HIREL–04/08 CPU_CYCLE (IDMA REQUEST CPU_CYCLE (IDMA REQUEST TS68EN360 IDMA_CYCLE IDMA_CYCLE e2v semiconductors SAS 2008 ...
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... Data-In Hold Time from Clock Low Clock High to Data-Out Valid (CPU Writes Data, Control, or Direction) Note spec Table 7-4. Figure 7-37. PIP Rx (Interlock Mode) DATA OUT STRBO (OUTPUT) STRBI (INPUT) e2v semiconductors SAS 2008 Figure 7-41) 25.0 MHz Min 0 2.5 – t3 1.5 1 CLKO1 – – ...
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... Figure 7-38. PIP Tx (Interlock Mode) DATA IN STRBI (INPUT) STRBO (OUTPUT) Figure 7-39. PIP Tx (Pulse Mode) DATA IN STBI (INPUT) STBO (OUTPUT) 52 0886C–HIREL–04/ TS68EN360 22 22 e2v semiconductors SAS 2008 ...
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... Figure 7-42 and Number Characteristic 35 Port C Interrupt Pulse Width Low (Edge Triggered Mode) 36 Minimum Time Between Active Edges Port C 37 Clock High to IOUT Valid (Slave Mode) 38 Clock High to RQOUT Valid (Slave Mode) e2v semiconductors SAS 2008 CPU WRITE S4 Figure 7-43) TS68EN360 ...
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... Number Characteristic 50 BRGO Rise and Fall Time 51 BRGO Duty Cycle 52 BRGO Cycle Figure 7-44. Baud Rate Generator Output Signals BRGOx 54 0886C–HIREL–04/ 25.0 MHz Min – TS68EN360 Figure 33.34 MHz Max Min Max Unit 10 – 7 e2v semiconductors SAS 2008 ...
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... TIN/TGATE Rise and Fall Time 62 TIN/TGATE Low Time 63 TIN/TGATE High Time 64 TIN/TGATE Cycle Time 65 CLKO1 High to TOUT Valid Figure 7-45. CPM General-purpose Timers CLKO1 (OUTPUT) 61 TIN/TGATE (INPUT) TOUT (OUTPUT) e2v semiconductors SAS 2008 Symbol t rf – – – TS68EN360 25.0 MHz 33.34 MHz ...
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... P+10 – – 15 – – 20 – 35 – 35 – – 15 – – 42 – 35 – 35 – – 12.5 – 16 – P+10 – – P+10 – – 30 – – 1 – 42 – 42 – 42 – 42 – – 0 – 0 e2v semiconductors SAS 2008 Unit MHz MHz L1TCLK ...
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... Figure 7-46. SI Receive Timing with Normal Clocking (DSC = 0) L1RCLK ( (INPUT) L1RCLK (FE =1, (INPUT) 75 L1RSYNC (INPUT) 73 L1RXD (INPUT) L1ST (4-1) (OUTPUT) e2v semiconductors SAS 2008 RFCD = BIT0 78 TS68EN360 79 57 0886C–HIREL–04/08 ...
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... Figure 7-47. SI Receive Timing with Double Speed Clocking (DSC = 1) L1RCLK ( (INPUT) L1RCLK ( (INPUT) 75 L1RSYNC (INPUT L1RXD (INPUT) L1ST (4-1) (OUTPUT) L1CLKO (OUTPUT 0886C–HIREL–04/08 72 83A 82 RFCD = BIT0 78 TS68EN360 79 e2v semiconductors SAS 2008 ...
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... Figure 7-48. SI Transmit Timing with Normal Clocking (DSC = 0) L1TCLK ( (INPUT) L1TCLK ( (INPUT) 75 L1TSYNC (OUTPUT) 73 80A L1TXD BIT0 (INPUT) 80 L1ST (4-1) (OUTPUT) e2v semiconductors SAS 2008 TFCD = 0 81 78A 78 TS68EN360 79 59 0886C–HIREL–04/08 ...
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... TFCD = B17 B16 B15 B14 B13 B12 B11 B10 B17 B16 B15 B14 B13 B12 B11 B10 TS68EN360 B27 B26 B25 B24 B23 B22 B21 B20 81 A B27 B26 B25 B24 B23 B22 B21 B20 e2v semiconductors SAS 2008 ...
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... CD1 Setup Time to RCLK1 Rising Edge Notes: 1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 3/1. 2. Also applies to CD and CTS hold time when they are used as external sync signals. e2v semiconductors SAS 2008 Figure 7-53) CLKO1 CLKO1 + 5 ns Figure ...
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... CD1 (SYNC- INPUT) Figure 7-52. SCC NMSI Transmit 102 TCLK1 TXD1 (OUTPUT) RTS1 (OUTPUT) CTS1 (INPUT) CTS1 (SYNC- INPUT) 62 0886C–HIREL–04/08 102 101 100 107 102 101 100 103 104 TS68EN360 108 107 104 105 107 e2v semiconductors SAS 2008 ...
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... Figure 7-53. HDLC BUS Timing 102 TCLK1 TXD1 (OUTPUT) RTS1 (OUTPUT) CTS1 (ECHO INPUT) e2v semiconductors SAS 2008 102 101 100 103 104 107 105 TS68EN360 104 63 0886C–HIREL–04/08 ...
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... MHz Max Min Max – 40 – 15 – 15 CLKO1 + – – – CLKO1 – – 20 – – 5 – – 10 – – 100 – 15 – 15 CLKO1 + – – – CLKO1 – – 1 – 20 – – 20 120 e2v semiconductors SAS 2008 Unit CLKO1 ns ns ...
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... Notes: 1. Transmit clock invert (TCI) bit in GSMR is set RENA is deasserted before TENA, or RENA is not asserted at all during transit, then CSL bit is set in the buffer descriptor at the end of frame transmission. e2v semiconductors SAS 2008 121 121 122 124 125 128 ...
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... Figure 7-59. SDACK Timing Diagram Note: SDACKx is asserted when the SDMA writes the received Ethernet frame into memory. 66 0886C–HIREL–04/ RRJCT (INPUT CLKO1 (OUTPUT) AS (OUTPUT) SDACKx (OUTPUT) TS68EN360 Bit # 1 Bit # 2 135 137 SDMA CYCLE 138 139 e2v semiconductors SAS 2008 136 ...
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... Figure 7-60. SMC Transparent 152 SMCLK TXD1 (OUTPUT) 154 155 SYNC1 154 RXD1 (INPUT) Note: This delay is equal to an integer number of “Character length” clocks e2v semiconductors SAS 2008 SMC Transparent. 152 151A 151 150 Note 1 155 TS68EN360 25.0 MHz 33.34 MHz Min Max ...
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... MHz 33.34 MHz Min Max Min Max 4 1024 4 1024 2 512 2 512 50 – 50 – 0 – 0 – – 20 – – 0 – 167 166 167 160 166 LSB IN MSB IN 164 "1" LSB OUT MSB OUT 166 e2v semiconductors SAS 2008 Unit tcyc tcyc ...
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... Slave SPIMISO Disable Time 179 Slave Data Valid (after SPICLK Edge) 180 Slave Data Hold Time (Outputs) 181 Rise Time: Input 182 Fall Time: Input e2v semiconductors SAS 2008 160 CI=0 161 CI=1 161 MSB IN 165 MSB OUT "1" 167 ...
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... LSB OUT UNDEF. MSB OUT 181 182 LSB IN MSB IN 174 182 181 172 173 181 182 180 178 SLAVE DATA UNDEF. LSB OUT 181 DATA LSB IN e2v semiconductors SAS 2008 ...
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... TCK Low to TDO High Impedance 14 TRST Assert Time 15 TRST Setup Time to TCK Low Figure 7-65. Test Clock Input Timing Diagram TCK (INPUT) 3 Figure 7-66. TRST Timing Diagram (INPUT) TRST (INPUT) e2v semiconductors SAS 2008 Figure 7-68 TCK 14 TS68EN360 25.0 MHz 33.34 MHz Min ...
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... Figure 7-68. Test Access Port Timing Diagram TCK (INPUT) TDI TMS (INPUT) TDO (OUTPUT) TDO (OUTPUT) TDO (OUTPUT) 72 0886C–HIREL–04/ INPUT DATA VALID 8 OUTPUT DATA VALID INPUT DATA VALID TS68EN360 OUTPUT DATA VALID OUTPUT DATA VALID OUTPUT DATA VALID e2v semiconductors SAS 2008 ...
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... Communications Processor Module (CPM) The CPM contains features that allow the QUICC to excel in communications and control applications. These features may be divided into three sub-groups: • Communications Processor (CP) • Two IDMA Controllers • Four General-purpose Timers e2v semiconductors SAS 2008 TS68EN360 73 0886C–HIREL–04/08 ...
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... CONTROL REGISTERS RECEIVER RECEIVE TRANSMIT CONTROL DATA DATA UNIT FIFO FIFO SHIFTER SHIFTER TS68EN360 SLOT TIME AND DEFER COUNTER RX CLOCK CLOCK GENERATOR TX CLOCK INTERNAL CLOCKS RTS = TENA TRANSMITTER CD = RENA CONTROL UNIT CTS = CLSN TXD e2v semiconductors SAS 2008 Figure 8- ...
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... First, the QUICC contains more general-purpose parallel I/O pins than the TS68302. However, the QUICC offers many more functions than even a 240-pin package would normally allow, resulting in more multifunctional pins than the TS68302 e2v semiconductors SAS 2008 TS68EN360 75 0886C–HIREL–04/08 ...
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... Microcircuits are prepared for delivery in accordance with MIL-PRF-38535 or e2v standards. 9.2 Certificate of Compliance e2v offers a certificate of compliances with each shipment of parts, affirming the products are in compli- ance either with MIL-STD-883 or e2v standard and guarantying the parameters not tested at temperature extremes for the entire temperature range. ...
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... Package Mechanical Data 11.1 241-pin – PGA (top view) T (BOTTOM VIEW e2v semiconductors SAS 2008 Inches Dim Min Max A 1.840 1.880 C 0.110 0.140 D 0.016 0.020 E 0.045 0.055 F 0.045 0.055 G 0.100 BASIC K 0.150 0.170 TS68EN360 Millimeters Min Max 46.74 47.75 2.79 3.56 ...
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... BSC 0.681 BSC V 34.41 34.75 1.355 W 0.25 0.75 0.0035 Y 17.30 BSC 0.681 BSC Z 0.12 0.13 0.005 AA 1.80 REF 0.071 REF AB 0.95 REF 0.037 REF e2v semiconductors SAS 2008 S MAX 1.250 1.250 0.163 0.012 0.154 0.010 0.007 0.021 1.37 1.37 0.0232 0.005 7 ...
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... For availability of the different versions, contact your local e2v sales office. 2. The letter X in the part number designates a "Prototype" product that has not been qualified by e2v. Reliability of a TSX part- number is not guaranteed and such part-number shall not be used in Flight Hardware. Product changes may still occur while shipping prototypes ...
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... AC Power Dissipation ........................................................................................... 16 7.5 AC Electrical Specifications Control Timing ......................................................... 17 7.6 External Capacitor For PLL .................................................................................. 18 7.7 Bus Operation AC Timing Specifications ............................................................. 19 7.8 Bus Operation – DRAM Accesses AC Timing Specification ................................ 35 e2v semiconductors SAS 2008 5.1.1 Terminal Connections ........................................................................... 11 5.1.2 Lead Material and Finish ....................................................................... 11 5.1.3 Package ................................................................................................ 11 7.6.1 Examples: ..............................................................................................18 ...
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... Hardware Compatibility Issues .............................................................. 75 8.5.3 Software Compatibility Issues ............................................................... 76 9 Preparation for Delivery ........................................................................ 76 9.1 Packaging ............................................................................................................. 76 9.2 Certificate of Compliance ..................................................................................... 76 10 Handling ................................................................................................. 76 11 Package Mechanical Data ..................................................................... 77 11.12 41-pin – PGA .................................................................................................... 77 11.22 40-pin – CERQUAD .......................................................................................... 78 12 Ordering Information ............................................................................. 79 ii 0886C–HIREL–04/08 TS68EN360 e2v semiconductors SAS 2008 ...
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... Document Revision History .................................................................. 79 Table of Contents ..................................................................................... i e2v semiconductors SAS 2008 TS68EN360 iii 0886C–HIREL–04/08 ...
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... Whilst e2v has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice. e2v accepts no liability beyond that set out in its stan- dard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with informa- tion contained herein ...