STM32W108HBU6 STMicroelectronics, STM32W108HBU6 Datasheet - Page 44

no-image

STM32W108HBU6

Manufacturer Part Number
STM32W108HBU6
Description
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32W108HBU6

Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Processing Unit
Microprocessor
Operating Supply Voltage (min)
1.18V
Operating Supply Voltage (typ)
1.25V
Operating Supply Voltage (max)
1.32V
Package Type
VFQFPN EP
Pin Count
40
Mounting
Surface Mount
Rad Hardened
No
Lead Free Status / Rohs Status
Supplier Unconfirmed

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STM32W108HBU6
Manufacturer:
ST
0
Part Number:
STM32W108HBU61TR
Manufacturer:
ST
0
Part Number:
STM32W108HBU63
Manufacturer:
ST
Quantity:
201
Part Number:
STM32W108HBU63TR
Manufacturer:
ST
0
Part Number:
STM32W108HBU64
Manufacturer:
ST
0
Part Number:
STM32W108HBU64TR
Manufacturer:
TDK
Quantity:
30 000
Part Number:
STM32W108HBU64TR
Manufacturer:
ST
0
System modules
44/208
31
15
31
Reserved
30
14
30
r
Bits [7:4] CLK_DIV (S/W name: SLEEPTMR_CLKDIV): Sleep timer prescaler setting
Bit 12 REVERSE (S/W name: SLEEPTMR_REVERSE):
Bit 11 ENABLE (S/W name: SLEEPTMR_ENABLE):
Bit 10 DBG_PAUSE (S/W name: SLEEPTMR_DBGPAUSE): Debug Pause
Watchdog restart register (WDOG_RESTART)
Write any value to this register to kick-start the watchdog.
Address:
Reset value:
Sleep timer configuration register (SLEEPTMR_CFG)
This register sets the various options for the Sleep timer.
Address:
Reset value:
Sleep timer count high register (SLEEPTMR_CNTH)
Address:
Reset value:
Bit 0 CLK_SEL (S/W name: SLEEPTMR_CLKSEL): Clock Select
29
13
29
REVE
RSE
0: count forward; 1: count backwards.
Only changes when ENABLE bit is set to ‘0’.
0: disable sleep timer; 1: enable sleep timer.
To change other register bits (REVERSE, CLK_DIV, CLK_SEL), this bit must be set to ‘0’.
Enabling/Disabling latency can be up 2 to 3 clock-periods of selected clock.
0: The timer continues working in Debug mode.
1: The timer is paused in Debug mode when the CPU is halted.
Divides clock by 2
Can only be changed when the ENABLE bit is set to ‘0’.
0: Calibrated 1kHz RC clock (default); 1: 32kHz
Can only be changed when the ENABLE bit is set to ‘0’.
28
12
28
rw
ENAB
27
11
LE
27
rw
0x4000 6008
0x0000 0000
0x4000 600C
0x0000 0400
0x4000 6010
0x0000 0000
DBG_
PAUS
26
10
26
rw
E
N
where N = 0 to 15.
25
25
9
Reserved
Doc ID 16252 Rev 7
r
24
24
8
Reserved
Reserved
23
23
7
22
22
6
CLK_DIV
rw
21
21
5
STM32W108CB, STM32W108HB
20
20
4
19
19
3
Reserved
18
18
2
r
17
17
1
CLK_S
EL
16
rw
16
0

Related parts for STM32W108HBU6