CY7C4231V-15AC Cypress Semiconductor Corp, CY7C4231V-15AC Datasheet - Page 2

• Manufacturer Part Number: CY7C4231V-15AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4231V-15AC

• Density: 16Kb
• Word Size: 9b
• Sync/async: Synchronous
• Expandable: Yes
• Package Type: TQFP
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Not Compliant

Functional Description
The CY7C42X1V provides four status pins: Empty, Full, Almost
Empty, Almost Full. The Almost Empty/Almost Full flags are program-
mable to single word granularity. The programmable flags default to
Empty 7 and Full 7.
The flags are synchronous, i.e., they change state relative to
either the Read Clock (RCLK) or the Write Clock (WCLK).
Selection Guide
Pin Definitions
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply
Current (mA)
Density
D
Q
WEN1
WEN2/LD
Dual Mode Pin
REN1, REN2
WCLK
RCLK
EF
FF
PAE
PAF
Signal Name
0 8
0 8
Data Inputs
Data Outputs
Write Enable 1
Write Enable 2
Load
Read Enable
Inputs
Write Clock
Read Clock
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
CY7C4421V
Description
64 x 9
(continued)
CY7C4201V
I/O
256 x 9
O
O
O
O
O
I
I
I
I
I
I
I
Commercial
Data Inputs for 9-bit bus.
Data Outputs for 9-bit bus.
The only write enable when device is configured to have programmable flags. Data is
written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH.
If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH transition
of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin
operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO
if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW
to write or read the programmable flag offsets.
Enables the device for Read operation.
The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH
and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-off-
set register.
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and the FIFO
is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag offset
register.
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value pro-
grammed into the FIFO.
When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed
into the FIFO.
CY7C4211V
512 x 9
CY7C42X1V-15
2
66.7
11
15
10
20
4
1
CY7C4221V
When entering or exiting the Empty and Almost Empty states,
the flags are updated exclusively by the RCLK. The flags de-
noting Almost Full and Full states are updated exclusively by
WCLK. The synchronous flag architecture guarantees that the
flags maintain their status for at least one cycle
All configurations are fabricated using an advanced 0.65
P-Well CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
1K x 9
CY7C4421V/4201V/4211V/4221V
Description
CY7C4231V
CY7C42X1V-25
CY7C4231V/4241V/4251V
2K x 9
40
15
25
15
20
6
1
CY7C4241V
4K x 9
CY7C42X1V-35
28.6
CY7C4251V
20
35
20
20
7
2
8K x 9