CY7C4231V-25AXC Cypress Semiconductor Corp, CY7C4231V-25AXC Datasheet
CY7C4231V-25AXC
Specifications of CY7C4231V-25AXC
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CY7C4231V-25AXC Summary of contents
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... RESET RS LOGIC THREE-ST ATE OUTPUTREGISTER Cypress Semiconductor Corporation Document #: 38-06010 Rev. *B CY7C4421V/4201V/4211V/4221VCY7C4231V/4241V/4251VLow-Voltage 64/256/512/1K/2K/4K/ Synchronous FIFOs CY7C4421V/4201V/4211V/4221V • Space saving 32-pin 7 mm × TQFP • 32-pin PLCC • Available in Pb-Free Packages Functional Description The CY7C42X1V are high-speed, low-power, FIFO memories with clocked read and write interfaces. All are nine bits wide. ...
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... All configurations are fabricated using an advanced 0.65µ P-Well CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V CY7C42X1V-25 CY7C42X1V- CY7C4231V CY7C4241V Description Unit MHz CY7C4251V Page ...
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... The contents of the offset registers can be read to the data outputs when WEN2/LD is LOW and both REN1 and REN2 are LOW. LOW-to-HIGH transitions of RCLK read register contents to the data outputs. Writes and reads should not be performed simultaneously on the offset registers. CY7C4231V/4241V/4251V Page ...
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... LOW when the number of unread words in the FIFO is greater than or equal to CY7C4421V (64 – m), CY7C4201V (256 – m), CY7C4211V (512 – m), CY7C4221V (1K – m), CY7C4231V (2K – m), CY7C4241V (4K – m), and CY7C4251V (8K – m). PAF is set HIGH by the LOW-to-HIGH transition of WCLK when the number of available memory locations is greater than m ...
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... WCLK. Empty Flag The Empty Flag (EF) will go LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of REN1 and REN2 synchronized to RCLK, i.e exclusively updated by each rising edge of RCLK. CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V CY7C4211V FF PAF ...
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... Figure 2. Block Diagram 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9 Low-Voltage Synchronous FIFO Document #: 38-06010 Rev. *B CY7C4421V/4201V/4211V/4221V RESET (RS Read Enable 2 (REN2) Memory Used in a Width-Expansion Configuration CY7C4231V/4241V/4251V READ CLOCK (RCLK) READ ENABLE 1 (REN1) OUTPUT ENABLE (OE) PROGRAMMABLE (PAE) EMPTY FLAG (EF) #1 CY7C42X1V EF EMPTY FLAG (EF) #2 DATA OUT (Q) ...
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... Com’l Description Test Conditions ° MHz 5.0V CC [ 510Ω GND Vth = 2.0V . OHZ CY7C4231V/4241V/4251V Ambient Temperature 0°C to +70°C –40° to +85°C 7C42X1V-25 7C42X1V-35 Max. Min. Max. Min. 2.4 2.4 0.4 0.4 5.0 2.0 5.0 2.0 −0.5 − ...
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... Empty Flag and Full Flag t Skew Time between Read Clock and Write Clock SKEW2 for Almost-Empty Flag and Almost-Full Flag Notes: 9. Pulse widths less than minimum values are not allowed. 10. Values guaranteed by design, not currently tested. Document #: 38-06010 Rev. *B CY7C4421V/4201V/4211V/4221V CY7C4231V/4241V/4251V 7C42X1V-15 Min. Max. 66 ...
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... CLKH CLKL t ENH NO OPERATION t REF [12] t SKEW1 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW1 CY7C4231V/4241V/4251V ENH NO OPERATION NO OPERATION t WFF t REF VALID DATA t OHZ Page ...
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... Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable flag offset registers. Document #: 38-06010 Rev. *B CY7C4421V/4201V/4211V/4221V RSS t RSS t RSS t RSF t RSF t RSF CY7C4231V/4241V/4251V t RSR t RSR t RSR [14 OE=0 Page ...
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... The Latency Timing applies only at the Empty Boundary (EF = LOW). SKEW1 17. The first word is available the cycle after EF goes HIGH, always. Document #: 38-06010 Rev. *B CY7C4421V/4201V/4211V/4221V D 1 [16] t FRL t SKEW1 t REF t OLZ t OE (maximum When t < minimum specification, t CLK SKEW1 SKEW1 CY7C4231V/4241V/4251V [17 (maximum) = either 2*t FRL CLK Page SKEW1 CLK ...
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... WEN1 t ENS t t ENS ENH WEN2 (if applicable) t RCLK t SKEW1 EF REN1, REN2 LOW OE DATA IN OUTPUT REGISTER Q – Document #: 38-06010 Rev. *B CY7C4421V/4201V/4211V/4221V [16] FRL t t REF REF t A CY7C4231V/4241V/4251V t DS DATAWRITE2 t ENH t ENS t t ENH ENS [16] t FRL t t SKEW1 DATA READ REF Page ...
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... WFF t ENH t A DATA READ t CLKL t t ENS ENH t t Note 19 ENS ENH [18] t PAE , then PAE may not change state until the next RCLK. CY7C4231V/4241V/4251V NO WRITE [11] t SKEW1 t t WFF WFF t ENH t ENS t A NEXT DATA READ WORDS Note 20 INFIFO t t ...
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... PAF offset = m. 23. 64–m words for CY7C4421V, 256-m words in FIFO for CY7C4201V, 512–m words for CY7C4211V, 1024–m words for CY7C4221V, 2048–m words for CY7C4231V, 4096–m words for CY7C4241V, 8192–m words for CY7C4251V. 24 the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge ...
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... Low Voltage Synchronous FIFO Speed (ns) Ordering Code 15 CY7C4221V-15AC CY7C4221V-15JC 25 CY7C4221V-25AC Low Voltage Synchronous FIFO Speed (ns) Ordering Code 15 CY7C4231V-15AC CY7C4231V-15JXC CY7C4231V-15JC 25 CY7C4231V-25AXC CY7C4231V-25AC CY7C4231V-25JC Document #: 38-06010 Rev. *B CY7C4421V/4201V/4211V/4221V t CLKL t ENH t A UNKNOWN PAE OFFSET LSB Package Name Package Type A32 32-Lead Thin Quad Flatpack ...
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... Package Type A32 32-Lead Thin Quad Flatpack A32 32-Lead Pb-Free Thin Quad Flatpack J65 32-Lead Plastic Leaded Chip Carrier A32 32-Lead Thin Quad Flatpack A32 32-Lead Pb-Free Thin Quad Flatpack CY7C4231V/4241V/4251V Operating Range Commercial Commercial Operating Range Commercial Commercial 51-85063-*B Page ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C4421V/4201V/4211V/4221V 32-Lead Plastic Leaded Chip Carrier J65 CY7C4231V/4241V/4251V 51-85002-*B Page ...
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... Fixed empty flag timing diagram Fixed switching waveform diagram typo ESH Added Pb-Free logo to top of front page Inserted industrial temperature range into operating range Added parts CY7C4251V-25AXC, CY7C4251V-15AXC, CY7C4241V-15AXC, CY7C4241V-15JXC, CY7C4241V-25XC, CY7C4231V-25AXC, CY7C4221V-15AI, CY7C4211V-15AXI, CY7C4201V-15AXC to ordering information. CY7C4231V/4241V/4251V Description of Change Page ...