CY7C4231V-15AC Cypress Semiconductor Corp, CY7C4231V-15AC Datasheet - Page 12

• Manufacturer Part Number: CY7C4231V-15AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4231V-15AC

• Density: 16Kb
• Word Size: 9b
• Sync/async: Synchronous
• Expandable: Yes
• Package Type: TQFP
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Not Compliant

Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as described
in Table 1 or the default values are used, the programmable
Almost Empty Flag (PAE) and programmable Almost Full Flag
(PAF) states are determined by their corresponding offset reg-
isters and the difference between the read and write pointers.
Table 1. Writing the Offset Registers
Note:
22. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
LD
0
0
1
1
8
8
8
8
WEN
64 x 9
0
1
0
1
6
6
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
WCLK
8
8
8
8
[22]
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
7
7
2K x 9
0
0
0
0
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
No Operation
Write Into FIFO
No Operation
2
2
(MSB)
(MSB)
000
000
8
8
8
8
Figure 1. Offset Register Location and Default Values
256 x 9
Selection
Empty Offset (LSB) Reg.
Default Value = 007h
7
7
Full Offset (LSB) Reg
Default Value = 007h
0
0
0
0
8
8
8
8
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
7
7
0
0
0
0
4K x 9
3
3
12
(MSB)
(MSB)
0000
0000
8
8
8
8
The number formed by the empty offset least significant bit
register and empty offset most significant register is referred
to as n and determines the operation of PAE. PAE is synchro-
nized to the LOW-to-HIGH transition of RCLK by one flip-flop
and is LOW when the FIFO contains n or fewer unread words.
PAE is set HIGH by the LOW-to-HIGH transition of RCLK when
the FIFO contains (n+1) or greater unread words.
The number formed by the full offset least significant bit regis-
ter and full offset most significant bit register is referred to as
m and determines the operation of PAF. PAE is synchronized
to the LOW-to-HIGH transition of WCLK by one flip-flop and is
set LOW when the number of unread words in the FIFO is
greater than or equal to CY7C4421V (64
(256
CY7C4231V (2K
CY7C4251V (8K
transition of WCLK when the number of available memory lo-
cations is greater than m.
512 x 9
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
7
7
CY7C4421V/4201V/4211V/4221V
0
0
0
0
m), CY7C4211V (512 – m), CY7C4221V (1K
8
8
8
8
(MSB)
CY7C4231V/4241V/4251V
(MSB)
m). PAF is set HIGH by the LOW-to-HIGH
0
0
0
0
0
0
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
7
7
m), CY7C4241V (4K
8K x 9
4
4
8
8
8
8
(MSB)
(MSB)
00000
00000
Empty Offset (LSB) Reg.
Default Value = 007h
Full Offset (LSB) Reg
Default Value = 007h
1K x 9
7
7
0
0
0
0
1
1
(MSB)
(MSB)
m), CY7C4201V
00
00
m), and
0
0
0
0
m),