AD5063BRMZ Analog Devices Inc, AD5063BRMZ Datasheet - Page 7

• Manufacturer Part Number: AD5063BRMZ
• Description: IC DAC 16BIT 2.7-5.5V 10-MSOP
• Manufacturer: Analog Devices Inc
• Series: nanoDAC™r

Specifications of AD5063BRMZ

• Data Interface: Serial, SPI™
• Settling Time: 4µs
• Number Of Bits: 16
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resolution (bits): 16bit
• Sampling Rate: 333kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Supply Current: 650µA
• Digital Ic Case Style: SOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
DIN
V
V
V
INV
R
AGND
DACGND
SYNC
SCLK
DD
REF
OUT
FB
Description
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and V
Reference Voltage Input.
Analog Output Voltage from DAC.
Connected to the Internal Scaling Resistors of the DAC. Connect the INV pin to the external op amp’s inverting
input in bipolar mode.
Feedback Resistor. In bipolar mode, connect this pin to the external op amp circuit.
Ground Reference Point for Analog Circuitry.
Ground Input to the DAC.
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When
SYNC goes low, it enables the input shift register, and data is then transferred in on the falling edges of the
following clocks. The DAC is updated following the 24
which case the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates of up to 30 MHz.
V
V
V
DIN
OUT
REF
INV
DD
Figure 3. Pin Configuration
4
1
2
3
5
Rev. C | Page 7 of 20
(Not to Scale)
AD5063
TOP VIEW
10
9
8
7
6
SCLK
SYNC
DACGND
AGND
R
FB
th
clock cycle unless SYNC is taken high before this edge, in
DD
should be decoupled to GND.
AD5063