MAX5874EGK+D Maxim Integrated Products, MAX5874EGK+D Datasheet - Page 11

• Manufacturer Part Number: MAX5874EGK+D
• Description: IC DAC 14BIT 200MSPS DUAL 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX5874EGK+D

• Settling Time: 14ns
• Number Of Bits: 14
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 300mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The TORB input selects between two’s-complement or
binary digital input data. Set TORB to a CMOS-logic-
high level to indicate a two’s-complement input format.
Set TORB to a CMOS-logic-low level to indicate a binary
input format.
The DORI input selects between a dual-port (parallel) or
single-port (interleaved) DAC. Set DORI high to configure
the MAX5874 as a dual-port DAC. Set DORI low to con-
figure the MAX5874 as a single-port DAC. In dual-port
mode, connect SELIQ to ground.
The MAX5874 latches input data on the rising edge of
the clock in a user-selectable two’s-complement or
binary format. A logic-high voltage on TORB selects
two’s-complement and a logic-low selects offset
binary format.
The MAX5874 includes a single-ended, CMOS-compati-
ble XOR input. Input data (all bits) are compared with the
Figure 2. Reference Architecture, Internal Reference
Configuration
Table 2. DAC Output Code Table
00 0000 0000 0000 10 0000 0000 0000
01 1111 1111 1111 00 0000 0000 0000 I
11 1111 1111 1111 01 1111 1111 1111
I
CMOS DAC Inputs (A13/B13–A0/B0, XOR, SELIQ)
REF
1µF
OFFSET
BINARY
I
= V
REF
14-Bit, 200Msps, High-Dynamic-Performance,
REFIO
DIGITAL INPUT CODE
R
/ R
SET
SET
Input Data Format Select (TORB, DORI )
CMOS-Compatible Digital Inputs
REFIO
FSADJ
DACREF
10kΩ
REFERENCE
______________________________________________________________________________________
1.2V
COMPLEMENT
TWO’S
CURRENT-SOURCE
ARRAY DAC
OUTFS
OUT_P
I
OUTFS
0
/ 2 I
OUTIP
OUTIN
OUTFS
OUT_N
I
Dual DAC with CMOS Inputs
OUTFS
0
/ 2
bit applied to XOR through exclusive-OR gates. Pulling
XOR high inverts the input data. Pulling XOR low leaves
the input data noninverted. By applying a previously
encoded pseudo-random bit stream to the data input and
applying decoding to XOR, the digital input data can be
decorrelated from the DAC output, allowing for the trou-
bleshooting of possible spurious or harmonic distortion
degradation due to digital feedthrough on the printed
circuit board (PCB).
A13/B13–A0/B0, XOR, and SELIQ are latched on the ris-
ing edge of the clock. In single-port mode (DORI pulled
low) a logic-high signal on SELIQ directs the B13–B0
data onto the I-DAC inputs. A logic-low signal at SELIQ
directs data to the Q-DAC inputs. In dual-port (parallel)
mode (DORI pulled high), data on pins A13–A0 are
directed onto the Q-DAC inputs and B13–B0 are directed
onto the I-DAC inputs.
The MAX5874 also features an active-high power-
down mode that reduces the DAC’s digital current
consumption from 22mA to less than 2µA and the ana-
log current consumption from 77mA to less than 2µA.
Set PD high to power down the MAX5874. Set PD low
for normal operation.
When powered down, the power consumption of the
MAX5874 is reduced to less than 14µW. The MAX5874
requires 10ms to wake up from power-down and enter a
fully operational state. The PD integrated pulldown resistor
activates the MAX5874 if PD is left floating.
Figure 3. Simplified Analog Output Structure
SWITCHES
CURRENT
AV
DD
CURRENT
SOURCES
Power-Down Operation (PD)
I
OUT
OUTIN OUTIP
I
OUT
11