MAX5590BEUG+ Maxim Integrated Products, MAX5590BEUG+ Datasheet - Page 9

• Manufacturer Part Number: MAX5590BEUG+
• Description: IC DAC 12BIT OCTAL BUFF 24-TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5590BEUG+

• Settling Time: 3µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 8
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Resolution: 12 bit
• Interface Type: Serial (SPI)
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Current: 3.2 mA
• Voltage Reference: External
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2)
(DV
Note 7: In some daisy-chain modes, data is required to be clocked in on one clock edge and the shifted data clocked out on the fol-
Note 8: The falling edge of DSP starts a DSP-type bus cycle, provided that CS is also active low to select the device. DSP active low
SCLK Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Fall to SCLK Fall Setup Time
DSP Fall to SCLK Fall Setup Time
SCLK Fall to CS Rise Hold Time
SCLK Fall to CS Fall Delay
SCLK Fall to DSP Fall Delay
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
SCLK Rise to DOUT_ Valid
Propagation Delay
SCLK Fall to DOUT_ Valid
Propagation Delay
CS Rise to SCLK Fall Hold Time
CS Pulse-Width High
DSP Pulse-Width High
DSP Pulse-Width Low
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1,
and UPIO Modes
DOUTRB Tri-State Time from CS
Rise
DOUTRB Tri-State Enable Time
from 8th SCLK Fall
LDAC Pulse-Width Low
LDAC Effective Delay
CLR, MID, SET Pulse-Width Low
GPO Output Settling Time
GPO Output High-Impedance
Time
DD
= 1.8V to 5.25V, V
lowing edge. In the case of a 1/2 clock-period delay, it is necessary to increase the minimum high/low clock times to 25ns
(2.7V) or 50ns (1.8V).
and CS active low must overlap by a minimum of 10ns (2.7V) or 20ns (1.8V). CS can be permanently low in this mode of
operation.
PARAMETER
Buffered, Fast-Settling, Octal, 12/10/8-Bit,
_______________________________________________________________________________________
AGND
= 0V, V
SYMBOL
DGND
t
DSPWL
t
f
t
t
t
t
t
t
t
DRBZ
t
SCLK
t
t
t
t
t
t
t
t
CSW
DSW
CMS
t
t
CSH
t
t
DO1
DO2
DOZ
t
GPZ
CSS
DSS
CS0
DS0
CS1
ZEN
LDL
LDS
CH
DH
CL
DS
GP
= 0V, T
1.8V < DV
(Note 7)
(Note 7)
C
mode
C
MICROWIRE and SPI modes 0 and 3
(Note 8)
C
in high impedance
C
in high impedance
C
UPIO_ driven out of tri-state
Figure 5
Figure 6
Figure 5
Figure 6
L
L
L
L
L
A
= 20pF, UPIO_ = DOUTDC1 or DOUTRB
= 20pF, UPIO_ = DOUTDC0 mode
= 20pF, from end of write cycle to UPIO_
= 20pF, from rising edge of CS to UPIO_
= 20pF, from 8th falling edge of SCLK to
= T
MIN
DD
to T
< 5.25V
CONDITIONS
MAX
, unless otherwise noted.)
Voltage-Output DACs
MIN
200
40
40
20
20
10
15
20
20
90
40
40
40
40
0
5
0
TYP
MAX
200
200
200
10
60
60
40
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9