MAX5590BEUG+ Maxim Integrated Products, MAX5590BEUG+ Datasheet
MAX5590BEUG+
Specifications of MAX5590BEUG+
Related parts for MAX5590BEUG+
MAX5590BEUG+ Summary of contents
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... SPI-/QSPI-/MICROWIRE-/DSP- Compatible Serial Interface o Glitch-Free Outputs Power Up to Zero Scale, Midscale, or Full Scale Controlled by PU Pin o Unity-Gain or Force-Sense-Configured Output Buffers Applications PART MAX5590AEUG+* MAX5590BEUG+ MAX5591AEUI+* MAX5591BEUI+ MAX5592EUG+ MAX5593EUI+ MAX5594EUG+ MAX5595EUI+ * Future product—contact factory for availability. Specifications are preliminary. ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs ABSOLUTE MAXIMUM RATINGS ........................................................................± AGND to DGND ..................................................................±0. AGND, DGND.............................................-0. AGND, DGND ............................................-0.3V to +6V DD FB_, OUT_, REF to AGND ........-0.3V ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, ELECTRICAL CHARACTERISTICS (continued) (AV = 2.7V to 5.25V 1. 4.5V to 5.25V 10kΩ 100pF (Note 1) PARAMETER SYMBOL Power-Supply Rejection ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs ELECTRICAL CHARACTERISTICS (continued) (AV = 2.7V to 5.25V 1. 4.5V to 5.25V 10kΩ 100pF (Note 1) PARAMETER SYMBOL ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, ELECTRICAL CHARACTERISTICS (continued) (AV = 2.7V to 5.25V 1. 4.5V to 5.25V 10kΩ 100pF (Note 1) PARAMETER SYMBOL POWER REQUIREMENTS ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V, 5V Logic) (Figure 1) (DV = 2.7V to 5.25V 0V AGND DGND PARAMETER SYMBOL SCLK Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1) (DV = 1.8V to 5.25V 0V AGND DGND PARAMETER SYMBOL SCLK Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SCLK Rise Setup ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V, 5V Logic) (Figure 2) (DV = 2.7V to 5.25V 0V AGND DGND PARAMETER SYMBOL SCLK Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2) (DV = 1.8V to 5.25V 0V AGND DGND PARAMETER SYMBOL SCLK Frequency SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SCLK Fall Setup ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs ( 5V 4.096V REF L noted.) INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (12-BIT B-GRADE -4 0 1024 2048 ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit 4.096V REF L noted.) DIFFERENTIAL NONLINEARITY vs. TEMPERATURE (12-BIT) 0.2 0.1 0 -0.1 B-GRADE MIDSCALE -0.2 -40 - TEMPERATURE (°C) SUPPLY CURRENT ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs ( 5V 4.096V REF L noted.) MAJOR-CARRY TRANSITION GLITCH MAX5590-95 toc19 CS 5V/div OUT_ 2mV/div 250ns/div REFERENCE INPUT BANDWIDTH -10 -15 -20 V ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, PIN MAX5590 MAX5591 NAME MAX5592 MAX5593 MAX5594 MAX5595 AGND 3 3 OUTA 4, 8, 17, 21 — N. OUTB 6 7 OUTC 7 10 OUTD ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs SERIAL SCLK INTERFACE CONTROL DIN DSP 16-BIT SHIFT REGISTER UPIO1 UPIO1 AND UPIO2 UPIO2 POWER-DOWN LOGIC LOGIC AND REGISTER DECODE CONTROL PU INPUT REGISTER A INPUT REGISTER H REF 14 ______________________________________________________________________________________ ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit SERIAL SCLK INTERFACE CONTROL DIN DSP 16-BIT SHIFT REGISTER UPIO1 UPIO1 AND UPIO2 UPIO2 POWER-DOWN LOGIC LOGIC AND REGISTER DECODE CONTROL PU INPUT REGISTER A INPUT REGISTER H REF ______________________________________________________________________________________ Voltage-Output DACs Functional ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs Detailed Description The MAX5590–MAX5595 octal, 12/10/8-bit, voltage-out- put DACs offer buffered outputs and a 3µs maximum settling time at the 12-bit level. The DACs operate from a single 2.7V to 5.25V analog supply and ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Table 1. Serial Write Data Format MSB CONTROL BITS D11 D10 SCLK DIN CS t CSW DOUTDC1* DOUTDC0 OR DOUTRB* *UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs Serial-Interface Programming Commands Tables 2a, 2b, and 2c provide all of the serial-interface programming commands for the MAX5590–MAX5595. Table 2a shows the basic DAC programming com- mands, Table 2b gives the advanced-feature program- ming ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, ______________________________________________________________________________________ Voltage-Output DACs 19 ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs 20 ______________________________________________________________________________________ ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, ______________________________________________________________________________________ Voltage-Output DACs 21 ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs IDA_0 IDB_0 IDA_1 IDB_1 IDA_2 IDB_2 IDA_3 IDB_3 IDA_4 IDB_4 IDA_5 IDB_5 IDA_6 IDB_6 IDA_7 IDB_7 IDA_8 IDB_8 IDA_9 IDB_9 IDA_10 IDB_10 IDA_11 IDB_11 DDA_0 DDB_0 DDA_1 DDB_1 DDA_2 DDB_2 DDA_3 DDB_3 DDA_4 DDB_4 ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, DAC Programming Examples: To load input register A from the shift register, leaving DAC register A unchanged (DAC output unchanged), use the command in Table 3. The MAX5590–MAX5595 can load all of the input regis- ters ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs Shutdown-Mode Bits (PD_0, PD_1) Use the shutdown-mode bits and control bits to shut down each DAC independently. The shutdown- mode bits determine the output state of the selected channels. The shutdown-control bits put the ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Settling-Time-Mode Write Example: To configure DACA and DACD into FAST mode and DACB and DACC into SLOW mode, use the command in Table 13. To read back the settling-time-mode bits, use the com- mand in Table ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs UPIO Bits (UPSL1, UPSL2, UP0–UP3) The MAX5590–MAX5595 provide two user-programma- ble input/output (UPIO) ports: UPIO1 and UPIO2. These ports have 15 possible configurations, as shown in Table 22. UPIO1 and UPIO2 can be programmed ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, UPIO Configuration Table 22 lists the possible configurations for UPIO1 and UPIO2. UPIO1 and UPIO2 use the selected function when configured by the UP3–UP0 configuration bits. LDAC controls the loading of the DAC registers. When LDAC ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs t LDL LDAC TOGG PDL t CMS CLR, MID, OR SET OUT_ PDL AFFECTS DAC OUPTUTS (V ) ONLY IF DACS WERE PREVIOUSLY SHUT DOWN. OUT_ Figure 5. Asynchronous Signal Timing ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, UPIO1 and UPIO2 can each be configured as a gener- al-purpose input (GPI), a general-purpose output low (GPOL general-purpose output high (GPOH). The GPI can serve to detect interrupts from µPs or micro- controllers. ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Voltage-Output DACs Applications Information Figure 7 shows the unity-gain MAX5590 in a unipolar output configuration. Table 24 lists the unipolar out- put codes. The MAX5590 outputs can be configured for bipolar operation, as shown in Figure ...
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Buffered, Fast-Settling, Octal, 12/10/8-Bit, Power-Supply and Layout Considerations Bypass the analog and digital power supplies by using a 10µF capacitor in parallel with a 0.1µF capacitor to AGND and DGND (Figure 10). Minimize lead lengths to reduce lead inductance. Use ...
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... OUTD 7 N. SCLK 10 DIN 11 DSP 12 TSSOP Selector Guide OUTPUT PART BUFFER CO NFIGUR ATION MAX5590AEUG+ Unity Gain MAX5590BEUG+ Unity Gain MAX5591AEUI+ Force Sense MAX5591BEUI+ Force Sense MAX5592EUG+ Unity Gain MAX5593EUI+ Force Sense MAX5594EUG+ Unity Gain MAX5595EUI+ Force Sense 32 ______________________________________________________________________________________ AV 24 REF AGND ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 33 © 2010 Maxim Integrated Products ...