AD9717BCPZ Analog Devices Inc, AD9717BCPZ Datasheet - Page 36

• Manufacturer Part Number: AD9717BCPZ
• Description: IC DAC DUAL 14BIT LO PWR 40LFCSP
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9717BCPZ

• Data Interface: Serial
• Number Of Bits: 14
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 86mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Resolution (bits): 14bit
• Sampling Rate: 125MSPS
• Input Channel Type: Parallel, Serial
• Supply Current: 11mA
• Digital Ic Case Style: CSP
• No. Of Pins: 40
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9714/AD9715/AD9716/AD9717
SPI REGISTER DESCRIPTIONS
Reading these registers returns previously written values for all defined register bits, unless otherwise noted.
Table 14.
Register
SPI Control
Power-Down
Data Control
I DAC Gain
Address
0x00
0x01
0x02
0x03
Bit
6
5
4
7
6
5
4
3
2
1
0
7
5
4
3
2
1
0
5:0
Name
LSBFIRST
Reset
LNGINS
LDOOFF
LDOSTAT
PWRDN
Q DACOFF
I DACOFF
QCLKOFF
ICLKOFF
EXTREF
TWOS
IFIRST
IRISING
SIMULBIT
DCI_EN
DCOSGL
DCODBL
I DACGAIN[5:0]
Description
0 (default): MSB first, per SPI standard.
1: LSB first, per SPI standard.
Note that the user must always change the LSB/MSB order in single-byte
instructions to avoid erratic behavior due to bit order errors.
Execute software reset of SPI and controllers, reload default register values except
Register 0x00.
1: sets software reset; write 0 on the next (or any following) cycle to release reset.
0 (default): the SPI instruction word uses a 5-bit address.
1: the SPI instruction word uses a 13-bit address.
0 (default): LDO voltage regulator on.
1: turns core LDO voltage regulator off.
0: indicates that the core LDO voltage regulator is off.
1 (default) : indicates that the core LDO voltage regulator is on.
0 (default): all analog and digital circuitry and SPI logic are powered on.
1: powers down all analog and digital circuitry except for SPI logic.
0 (default): turns on Q DAC output current.
1: turns off Q DAC output current.
0 (default): turns on I DAC output current.
1: turns off I DAC output current.
0 (default): turns on Q DAC clock.
1: turns off Q DAC clock.
0 (default): turns on I DAC clock.
1: turns off I DAC clock.
0 (default): turns on internal voltage reference.
1: powers down internal voltage reference (external reference required).
0 (default): unsigned binary input data format.
1: twos complement input data format.
0: pairing of data—Q first of pair on data input pads.
1 (default): pairing of data—I first of pair on data input pads.
0: Q data latched on DCLKIO rising edge.
1 (default): I data latched on DCLKIO rising edge.
0 (default): allows simultaneous input and output enable on DCLKIO.
1: disallows simultaneous input and output enable on DCLKIO.
Controls the use of the DCLKIO pad for data clock input.
0: data clock input disabled.
1 (default): data clock input enabled.
Controls the use of the DCLKIO pad for data clock output.
0 (default): data clock output disabled.
1: data clock output enabled; regular strength driver.
Controls the use of the DCLKIO pad for data clock output.
0 (default): DCODBL data clock output disabled.
1: DCODBL data clock output enabled; paralleled with DCOSGL for 2× drive
current.
DAC I fine gain adjustment; alters the full-scale current as shown in Figure 100.
Default IDACGAIN = 0x00.
Rev. A | Page 36 of 80