AD5273BRJ50-R2 Analog Devices Inc, AD5273BRJ50-R2 Datasheet - Page 15

• Manufacturer Part Number: AD5273BRJ50-R2
• Description: IC DGTL POT 50K 64POS SOT23-8
• Manufacturer: Analog Devices Inc

Specifications of AD5273BRJ50-R2

• Rohs Status: RoHS non-compliant
• Taps: 64
• Resistance (ohms): 50K
• Number Of Circuits: 1
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-8
• Resistance In Ohms: 50K
• For Use With: AD5273EVAL - BOARD EVAL FOR AD5273
• Other names: AD5273BRJ50-R2; AD5273BRJ50-R2TR

Unlike rheostat mode where the absolute tolerance is high,
potentiometer mode yields an almost ratiometric function of
D/63 with a relatively small error contributed by the R
Therefore, the tolerance effect is almost cancelled. Although the
step resistor, R
ent temperature coefficients, the ratiometric adjustment also
reduces the overall temperature coefficient effect to 5 ppm/°C,
except at low value codes where R
Potentiometer mode includes op amp feedback resistor networks
and other voltage scaling applications. Terminal A, Terminal W,
and Terminal B can in fact be input or output terminals, provided
that |V
ESD PROTECTION
Digital inputs SDA and SCL are protected with a series input
resistor and parallel Zener ESD structures (see Figure 36).
TERMINAL VOLTAGE OPERATING RANGE
There are also ESD protection diodes between V
RDAC terminals. The V
voltage boundary conditions (see Figure 37). Supply signals
present on Terminal A, Terminal B, and Terminal W that exceed
V
POWER-UP/POWER-DOWN SEQUENCES
Because of the ESD protection diodes, it is important to power
V
and Terminal W. Otherwise, the diode is forward-biased such that
V
circuits. The ideal power-up sequence is in the following order:
GND, V
V
powered after V
POWER SUPPLY CONSIDERATIONS
To minimize the package pin count, both OTP and normal opera-
ting voltage supplies are applied to the same V
AD5273. The AD5273 employs fuse link technology that requires
from 5 V to 5.5 V for the 1 kΩ (DD8) and 10 kΩ (DD9) options,
or from 4.75 V to 5.25 V for the 50 kΩ (DYG) and 100 kΩ (DYH)
options, for blowing the internal fuses to achieve a given setting,
but normal V
DD
DD
DD
A
, V
first before applying any voltages to Terminal A, Terminal B,
is powered unintentionally and can affect the rest of the user’s
are clamped by the internal forward-biased diodes.
B
, V
AB
DD
|, |V
W
, digital inputs, and V
, and digital inputs is not important as long as they are
Figure 37. Maximum Terminal Voltages Set by V
WA
DD
S
, and CMOS switch resistor, R
|, and |V
Figure 36. ESD Protection of Digital Pins
DD
can be in the range of 2.7 V to 5.5 V after
. Similarly, V
WB
DD
340Ω
| do not exceed V
of AD5273 therefore defines their
DD
A
LOGIC
/V
W
should be powered down last.
B
/V
dominates.
W
. The order of powering
V
A
W
B
GND
DD
DD
DD
W
to GND.
, have very differ-
terminal of the
DD
and the
DD
W
terms.
Rev. H | Page 15 of 24
completing the fuse programming process. As a result, dual
voltage supplies and isolation are needed if the system V
outside the required V
programming supply (either an on-board regulator or rack-mount
power supply) must be rated at 5 V to 5.5 V for the 1 kΩ (DD8)
and 10 kΩ (DD9) options, or at 4.75 V to 5.25 V for the 50 kΩ (DYG)
and 100 kΩ (DYH) options, and be capable of sourcing 100 mA
for 400 ms. When fuse programming is completed, the V
supply can be removed to allow normal operation of 2.7 V to 5.5 V;
the device then reduces the current consumption to the μA range.
When operating systems at 2.7 V, use of the bidirectional low
threshold P-Ch MOSFETs is recommended for the supply’s
isolation. As shown in Figure 38, this assumes that the 2.7 V
system voltage is applied first and that the P1 and P2 gates are
pulled to ground, thus turning on P1 first and then P2. As a
result, V
setting is found, the factory tester applies the V
the V
The OTP command should be executed at this time to program
the AD5273 while the 2.7 V source is protected. Once the fuse
programming is complete, the tester withdraws the V
the AD5273’s setting is fixed permanently.
The AD5273 achieves the OTP function through blowing
internal fuses. Users should always apply the recommended
OTP programming voltage at the first fuse programming
attempt. Failure to comply with this requirement can lead to a
change in fuse structures, rendering programming inoperable.
Care should be taken when SCL and SDA are driven from a low
voltage logic controller. Users must ensure that the logic high
level is between 0.7 × V
Different Voltages Operation section.
Poor PCB layout introduces parasitics that can affect fuse program-
ming. Therefore, it is recommended to add a 10 μF tantalum
capacitor in parallel with a 1 nF ceramic capacitor as close as
possible to the V
tors are important. This combination of capacitor values provides a
fast response and larger supply current handling with minimum
supply drop during transients. As a result, these capacitors increase
the OTP programming success by not inhibiting the proper energy
needed to blow the internal fuses. Additionally, C1 minimizes
transient disturbance and low frequency ripple, while C2 reduces
high frequency noise during normal operation.
Figure 38. OTP Supply Isolated from the 2.7 V Normal Operating Supply
DD
and the MOSFETs’ gates, thus turning off P1 and P2.
V
DD
DD_OTP
2.7V
of the AD5273 approaches 2.7 V. When the AD5273
10kΩ
R1
P1 = P2 = FDV302P, NDS0610
DD
APPLIES FOR OTP ONLY
pin. The type and value chosen for both capaci-
P1
DD_OTP
DD
P2
and V
range. For successful OTP, the fuse
C1
10mF
DD
. Refer to the Level Shift for
C2
0.1µF
V
AD5273
DD
DD_OTP
AD5273
to both
DD_OTP
DD
DD_OTP
is
and