TWR-AUDIO-SGTL Freescale Semiconductor, TWR-AUDIO-SGTL Datasheet - Page 8

• Manufacturer Part Number: TWR-AUDIO-SGTL
• Description: TWR SYS Audio Board
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of TWR-AUDIO-SGTL

• Kit Contents: TWR-AUDIO-SGTL Featuring SGTL5000 Low Power Stereo Codec, Printed Quick Start Guide
• Mcu Supported Families: K20, K50, MCF51Jx
• Kit Features: SGTL5000 Low Power Stereo Codec With Headphone
• Rohs Compliant: Yes
• Design Resources: TWR-AUDIO-SGTL Schematics
• Accessory Type: Module, Audio with CODEC
• Description/function: Audio CODECs
• Mounting Style: Press Fit
• Product: Audio Modules
• Features: SGTL5000 Low Power Stereo Codec With Headphone Amplifier, Stereo Line-in / Line-out On 3.5mm Jack
• Lead Free Status / Rohs Status: Details
• For Use With/related Products: Freescale Tower System

Table 5. Dynamic Electrical Characteristics
8
POWER UP TIMING
I2C BUS TIMING
SPI BUS TIMING
SPECIFICATIONS AND TIMING FOR THE I
Notes
SGTL500
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Time from all supplies powered up and SYS_MCLK present to initial
communication. See
I
I
I
I
I
I
I
I
SPI Serial Clock Frequency
SPI data input setup time
SPI data input hold time
SPI CTRL_CLK low time
SPI CTRL_CLK high time
SPI clock to chip select
SPI chip select to clock
SPI chip select low
SPI chip select high
Frequency of I
Frequency of I
I
I
I
2
2
2
2
2
2
2
2
2
2
2
C Serial Clock Frequency
C Start condition hold time
C Stop condition setup time
C Data input setup time to rising edge of CTRL_CLK
C Data input hold time from falling edge of CTRL_CLK (receiving data)
C Data input hold time from falling edge of CTRL_CLK (driving data)
C CTRL_CLK low time
C CTRL_CLK high time
S delay
S setup time
S hold time
1.
2.
3.
4.
5.
The SGTL5000 has an internal reset that is deasserted 8 SYS_MCLK cycles after all power rails have been brought up. After this time,
communication can start.
1.0μs represents 8 SYS_MCLK cycles at the minimum 8.0 MHz SYS_MCLK.
This section provides timing for the SGTL5000 while in I
This section provides timing for the SGTL5000 while in SPI mode (CTRL_MODE = 1)
The following are the specifications and timing for I
2
2
S_LRCLK
S_SCLK
(3)
(4)
See
See
Figure
Figure
Figure
4.
5.
Characteristic
6.
DYNAMIC ELECTRICAL CHARACTERISTICS
2
S PORT
(5)
See
2
S port. The timing applies to all formats.
Figure
2
C mode (CTRL_MODE = 0).
7.
Symbol
t
t
t
f
t
f
t
t
t
SPICLKH
I2CSTSU
I2CCLKH
SPI_CLK
SPICLKL
I2C_CLK
I2CCLKL
f
t
t
SPIDSU
t
t
I2CDSU
f
t
t
t
LRCLK
I2CSH
I2CDH
I2CDH
SPIDH
t
t
t
I2S_D
I2S_S
I2S_H
t
SCLK
t
CCS
CSC
CSL
CSH
PC
1.0
TBD
TBD
TBD
Min
150
150
125
360
300
100
5.0
10
10
60
20
20
20
10
10
-
-
-
-
(2)
Analog Integrated Circuit Device Data
32*f
64*f
Typ
LRCLK
LRCLK
–
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Freescale Semiconductor
Max
TBD
400
-96
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
MHz
kHz
kHz
kHz
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns