TWR-AUDIO-SGTL Freescale Semiconductor, TWR-AUDIO-SGTL Datasheet - Page 16

• Manufacturer Part Number: TWR-AUDIO-SGTL
• Description: TWR SYS Audio Board
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of TWR-AUDIO-SGTL

• Kit Contents: TWR-AUDIO-SGTL Featuring SGTL5000 Low Power Stereo Codec, Printed Quick Start Guide
• Mcu Supported Families: K20, K50, MCF51Jx
• Kit Features: SGTL5000 Low Power Stereo Codec With Headphone
• Rohs Compliant: Yes
• Design Resources: TWR-AUDIO-SGTL Schematics
• Accessory Type: Module, Audio with CODEC
• Description/function: Audio CODECs
• Mounting Style: Press Fit
• Product: Audio Modules
• Features: SGTL5000 Low Power Stereo Codec With Headphone Amplifier, Stereo Line-in / Line-out On 3.5mm Jack
• Lead Free Status / Rohs Status: Details
• For Use With/related Products: Freescale Tower System

POWER CONSUMPTION
Table 7. Power Consumption: V
PLL case, 32 ohm load on HP, Conditions: -100 dBFs signal
input, slave mode unless otherwise noted, paths tested as
indicated, unused paths turned off.
Table 8. Power Consumption: V
DIGITAL INPUT & OUTPUT
following formats: I
mode.
16
SGTL500
FUNCTIONAL DEVICE OPERATION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Playback (I
Playback with DAP ((I
Playback/Record (I
Record (ADC->I
Analog playback, CODEC bypassed (LINEIN->HP)
Standby, all analog power off
Playback with PLL (I
Playback (I
Playback with DAP ((I
Playback/Record (I
Record (ADC->I
Analog playback, CODEC bypassed (LINEIN->HP)
Standby, all analog power off
Playback with PLL (I
V
One I
DDD
2
derived internally @ 1.2 V, slave mode except for
S (Digital Audio) Port is provided which supports the
2
2
S->DAC->Headphone)
S->DAC->Headphone)
2
2
S)
S)
2
2
2
S, Left Justified, Right Justified, and PCM
S->DAC->Headphone, ADC->I
S->DAC->Headphone, ADC->I
2
2
S->DAC->HP)
S->DAC->HP)
2
2
S->DAP->DAC->Headphone)
S->DAP->DAC->Headphone)
MODE
MODE
DDA
DDA
FUNCTIONAL DEVICE OPERATION
=1.8 V, V
=3.3 V, V
DDIO
2
DDIO
2
S)
S)
=1.8 V
=3.3 V
V
V
DDD
DDD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TA2 silicon.
I
interface formats. The I2S_SCLK frequency, I2S_SCLK
polarity, I2S_DIN/DOUT data length, and I2S_LRCLK
polarity can all be change through the CHIP_I2S_CTRL
2
CURRENT CONSUMPTION (MA)
CURRENT CONSUMPTION (MA)
S, Left Justified, and Right Justified Modes
A further 0.5-1.0 mW reduction in power is expected with
I
2
S, Left Justified and Right Justified modes are stereo
V
0.019
V
3.45
4.49
4.67
2.90
1.91
0.04
3.92
2.54
3.59
3.71
2.29
1.48
3.01
DDA
DDA
Analog Integrated Circuit Device Data
V
V
0.002
0.067
0.067
0.343
0.296
0.039
0.002
1.10
1.06
0.89
2.17
2.76
0.9
0.9
DDIO
DDIO
Freescale Semiconductor
POWER (MW)
POWER(MW)
0.038
11.60
15.03
16.53
10.56
0.139
22.05
6.19
8.08
8.67
6.02
4.27
9.31
6.43