TWR-AUDIO-SGTL Freescale Semiconductor, TWR-AUDIO-SGTL Datasheet - Page 18

• Manufacturer Part Number: TWR-AUDIO-SGTL
• Description: TWR SYS Audio Board
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of TWR-AUDIO-SGTL

• Kit Contents: TWR-AUDIO-SGTL Featuring SGTL5000 Low Power Stereo Codec, Printed Quick Start Guide
• Mcu Supported Families: K20, K50, MCF51Jx
• Kit Features: SGTL5000 Low Power Stereo Codec With Headphone
• Rohs Compliant: Yes
• Design Resources: TWR-AUDIO-SGTL Schematics
• Accessory Type: Module, Audio with CODEC
• Description/function: Audio CODECs
• Mounting Style: Press Fit
• Product: Audio Modules
• Features: SGTL5000 Low Power Stereo Codec With Headphone Amplifier, Stereo Line-in / Line-out On 3.5mm Jack
• Lead Free Status / Rohs Status: Details
• For Use With/related Products: Freescale Tower System

PCM Mode
known as DSP mode). This mode is provided to allow
connectivity to external devices such as Bluetooth modules.
PCM mode differs from other interface formats presented in
I2S, Left Justified, and Right Justified
frame clock (I2S_LRCLK) does not represent a different
channel when high or low, but is a bit-wide pulse that marks
the start of a frame. Data is aligned such that the left channel
data is immediately followed by right channel data. Zero
padding is filled in for the remaining bits. The data and frame
DIGITAL AUDIO PROCESSING
(DAP) attached to the source select switch. The digitized
signal from the source select switch can be routed into the
DAP block for audio processing. The DAP has the following
5 sub blocks:
• Dual Input Mixer
18
SGTL500
FUNCTIONAL DEVICE OPERATION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
The I
The SGTL5000 contains a digital audio processing block
I2S_DIN, DOUT
I2S_DIN, DOUT
2
(SCLKFREQ = 1; MS = 1; SCLK_INV = 1; DLEN = 3; I2S_MODE = 2; LRALIGN = 0)
S port can also be configured into a PCM mode (also
(SCLKFREQ = 1; MS = 1; SCLK_INV = 1; DLEN = 3; I2S_MODE = 2; LRALIGN = 1)
I2S_LRCLK
I2S_LRCLK
I2S_SCLK
I2S_SCLK
L
n
L
L
n
(n-1)
L
(n-1)
Modes, in that the
PCM Format A
CHIP_I2S0_CTRL = 0x01F4
L
PCM Format B
0
CHIP_I2S0_CTRL = 0x01F6
L
0
R
n
R
n
Figure 11. PCM Formats
R
( n-1)
R
(n-1)
R
1
R
0
clock may be configured to clock in on the rising or falling
edge of Bit Clock.
SCLK bit following the I2S_LRCLK transition, as in I
PCM Format B signifies the data word beginning after the
I2S_LRCLK transition, as in Left Justified.
matter. The pulse can range from one cycle high to all but one
cycle high. In master mode, it will be driven one cycle high.
formats in master mode.
• Freescale Surround
• Freescale Bass Enhancement
• 7-Band Parameter EQ / 5-Band Graphic EQ / Tone Control
• Automatic Volume Control (AVC)
which the signal passes through these blocks.
R
L
0
PCM Format A signifies the data word beginning one
In slave mode, the pulse width of the I2S_LRCLK does not
Figures 11
n
(only one can be used at a time)
The block diagram in
L
L
n
( n-1)
L
(n-1)
shows a functional drawing of the different
L
0
L
0
Analog Integrated Circuit Device Data
Figure 12
R
n
R
n
R
(n-1)
R
(n-1)
shows the sequence in
Freescale Semiconductor
R
1
R
0
R
0
2
S Mode.