CY7C1412KV18-300BZXI Cypress Semiconductor Corp, CY7C1412KV18-300BZXI Datasheet - Page 25

• Manufacturer Part Number: CY7C1412KV18-300BZXI
• Description: CY7C1412KV18-300BZXI
• Manufacturer: Cypress Semiconductor Corp
• Series: -r

Specifications of CY7C1412KV18-300BZXI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 36M (2M x 18)
• Speed: 300MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 165-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Switching Characteristics
Over the Operating Range
Notes
Document Number: 001-57825 Rev. *D
Parameter
t
t
t
t
t
t
Setup Times
t
t
t
t
Hold Times
t
t
t
t
POWER
CYC
KH
KL
KHKH
KHCH
SA
SC
SCDDR
SD
HA
HC
HCDDR
HD
26. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250
27. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is
28. This part has a voltage regulator internally; t
Cypress
pulse levels of 0.25 V to 1.25 V, and output loading of the specified I
operated and outputs data with the output timings of that frequency range.
t
t
t
t
t
t
t
t
t
t
t
t
t
Consortium
KHKH
KHKL
KLKH
KHKH
KHCH
AVKH
IVKH
IVKH
DVKH
KHAX
KHIX
KHIX
KHDX
Parameter
V
K clock and C clock cycle time
Input clock (K/K; C/C) HIGH
Input clock (K/K; C/C) LOW
K clock rise to K clock rise and C to
C rise (rising edge to rising edge)
K/K clock rise to C/C clock rise
(rising edge to rising edge)
Address set-up to K clock rise
Control set-up to K clock rise
(RPS, WPS)
DDR control set-up to clock (K/K)
rise (BWS
D
Address hold after K clock rise
Control hold after K clock rise (RPS,
WPS)
DDR control hold after clock (K/K)
rise (BWS
D
[26, 27]
DD
[X:0]
[X:0]
(typical) to the first access
hold after clock (K/K) rise
set-up to clock (K/K) rise
0
0
, BWS
, BWS
Description
POWER
1
1
is the time that the power must be supplied above V
, BWS
, BWS
2
2
, BWS
, BWS
[28]
OL
3
3
/I
)
)
OH
and load capacitance shown in (a) of
1.20
1.20
1.35
Min Max Min Max Min Max Min Max Min Max
3.0
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
333 MHz
1
0
1.30
8.4
–
–
–
–
–
–
–
–
–
–
–
–
1.32
1.32
1.49
3.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
300 MHz
1
0
CY7C1410KV18, CY7C1425KV18
CY7C1412KV18, CY7C1414KV18
1.45
8.4
–
–
–
–
–
–
–
–
–
–
–
–
DD
minimum initially before initiating a read or write operation.
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
4.0
1.6
1.6
1.8
250 MHz
1
0
AC Test Loads and
8.4
1.8
–
–
–
–
–
–
–
–
–
–
–
–
5.0
2.0
2.0
2.2
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
200 MHz
1
0
Waveforms.
8.4
2.2
–
–
–
–
–
–
–
–
–
–
–
–
6.0
2.4
2.4
2.7
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
167 MHz

1
0
, V
DDQ
Page 25 of 32
8.4
2.7
–
–
–
–
–
–
–
–
–
–
–
–
= 1.5 V, input
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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