CY7C1412KV18-300BZXI Cypress Semiconductor Corp, CY7C1412KV18-300BZXI Datasheet - Page 11

• Manufacturer Part Number: CY7C1412KV18-300BZXI
• Description: CY7C1412KV18-300BZXI
• Manufacturer: Cypress Semiconductor Corp
• Series: -r

Specifications of CY7C1412KV18-300BZXI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, QDR II
• Memory Size: 36M (2M x 18)
• Speed: 300MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 165-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Truth Table
The truth table for CY7C1410KV18, CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 follow.
Write Cycle Descriptions
The write cycle description table for CY7C1410KV18 and CY7C1412KV18 follow.
Document Number: 001-57825 Rev. *D
Write cycle:
Load address on the rising edge of K;
input write data on K and K rising edges.
Read cycle:
Load address on the rising edge of K;
wait one and a half cycle; read data on C and C rising edges.
NOP: No operation
Standby: Clock stopped
Notes
BWS
NWS
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
3. Device powers up deselected with the outputs in a tristate condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. Ensure that when the clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging
8. Is based on a write cycle that was initiated in accordance with the
H
H
H
H
L
L
L
L
symmetrically.
different portions of a write cycle, as long as the setup and hold requirements are achieved.
0
0
/
BWS
NWS
H
H
H
H
L
L
L
L
1
1
/
L–H
L–H
L–H
L–H
K
–
–
–
–
Operation
L–H During the data portion of a write sequence 
L–H During the data portion of a write sequence 
L–H No data is written into the devices during this portion of a write operation.
L-H During the data portion of a write sequence 
K
–
–
–
–
During the data portion of a write sequence 
CY7C1410KV18 both nibbles (D
CY7C1412KV18 both bytes (D
CY7C1410KV18 both nibbles (D
CY7C1412KV18 both bytes (D
During the data portion of a write sequence 
CY7C1410KV18 only the lower nibble (D
CY7C1412KV18 only the lower byte (D
CY7C1410KV18 only the lower nibble (D
CY7C1412KV18 only the lower byte (D
During the data portion of a write sequence 
CY7C1410KV18 only the upper nibble (D
CY7C1412KV18 only the upper byte (D
CY7C1410KV18 only the upper nibble (D
CY7C1412KV18 only the upper byte (D
No data is written into the devices during this portion of a write operation.

represents rising edge.
Write Cycle Descriptions
Stopped
[17:0]
[17:0]
L-H
L-H
L-H
[7:0]
[7:0]
K
) are written into the device.
) are written into the device.
) are written into the device.
) are written into the device.
[8:0]
[8:0]
[17:9]
[17:9]
RPS WPS
[3:0]
[3:0]
[7:4]
[7:4]
table. NWS
X
H
X
L
Comments
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
CY7C1410KV18, CY7C1425KV18
CY7C1412KV18, CY7C1414KV18
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
[2, 8]
X
H
X
L
0
, NWS
D(A + 0) at K(t) 
Q(A + 0) at C(t + 1)  Q(A + 1) at C(t + 2) 
D = X
Q = high Z
Previous state
1
, BWS
0
DQ
, BWS
[2, 3, 4, 5, 6, 7]
1
, BWS
[17:9]
[17:9]
[8:0]
[8:0]
[7:4]
[7:4]
[3:0]
[3:0]
2
, and BWS
remains unaltered.
remains unaltered.
D(A + 1) at K(t) 
D = X
Q = high Z
Previous state
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
3
can be altered on
Page 11 of 32
DQ
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