AD7294BSUZ Analog Devices Inc, AD7294BSUZ Datasheet - Page 9

• Manufacturer Part Number: AD7294BSUZ
• Description: IC ADC 12BIT W/DAC/TEMP 64TQFP
• Manufacturer: Analog Devices Inc
• Type: ADC, DACr

Specifications of AD7294BSUZ

• Resolution (bits): 12 b
• Data Interface: Serial
• Sampling Rate (per Second): 22.22k
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -55°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Sampling Rate: 22.22kSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Digital: 4.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
I
AV
DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V; OFFSET IN x is floating, therefore, DAC output span = 0 V to 5 V; T
−40°C to +105°C, unless otherwise noted.
Table 4.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
C
1
2
Timing and Circuit Diagrams
SDA
SCL
2
SCL
1
2
3
4
5
6
7
8
9
10
11
See Figure 2.
C
b
C Serial Interface
b
DD
is the total capacitance in pF of one bus line. t
= DV
1
t
DD
9
= 4.5 V to 5.5 V, AGND = DGND = 0 V, V
CONDITION
Limit at T
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
0
0
300
20 + 0.1C
400
300
300
START
t
4
b
MIN
2
t
3
, T
MAX
t
10
R
t
and t
6
TO OUTPUT PIN
Unit
kHz max
µs min
µs min
µs min
µs min
ns min
µs max
µs min
µs min
µs min
µs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
Figure 2. I
F
are measured between 0.3 DV
Figure 3. Load Circuit for Digital Output
2
C-Compatible Serial Interface Timing Diagram
t
2
REF
Description
SCL clock frequency
SCL cycle time
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Capacitive load for each bus line
HIGH
LOW
HD,STA
SU,DAT
HD,DAT
HD,DAT
SU,STA
SU,STO
BUF
R
R
F
F
F
F
= 2.5 V internal or external; V
, rise time of SCL and SDA when receiving
, rise time of SCL and SDA when receiving (CMOS compatible)
, fall time of SDA when transmitting
, fall time of SDA when receiving (CMOS compatible)
, fall time of SCL and SDA when receiving
, fall time of SCL and SDA when transmitting
Rev. F | Page 9 of 48
, bus free time between a stop and a start condition
, SCL low time
, SCL high time
t
C
50pF
, setup time for repeated start
, start/repeated start condition hold time
, data setup time
, stop condition setup time
11
, data hold time
, data hold time
L
200µA
200µA
t
5
DD
and 0.7 DV
I
I
OL
OH
V
V
DD
CONDITION
REPEATED
OH
OL
.
START
(MAX)
(MIN) OR
t
7
DRIVE
t
4
= 2.7 V to 5.5 V; V
t
1
PP
= AV
DD
CONDITION
to 59.4 V;
STOP
t
8
AD7294
A
=