AD7294BSUZ Analog Devices Inc, AD7294BSUZ Datasheet - Page 32

• Manufacturer Part Number: AD7294BSUZ
• Description: IC ADC 12BIT W/DAC/TEMP 64TQFP
• Manufacturer: Analog Devices Inc
• Type: ADC, DACr

Specifications of AD7294BSUZ

• Resolution (bits): 12 b
• Data Interface: Serial
• Sampling Rate (per Second): 22.22k
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -55°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Sampling Rate: 22.22kSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Digital: 4.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7294
POWER-DOWN REGISTER (0x0A)
The power-down register is an 8-bit read/write register that
powers down various sections on the AD7294 device. On
power-up, the default value for the power-down register is 0x30.
The content of the power-down register is provided in Table 27.
Table 27. Power-Down Register Description
Bit
D7
D6
D5
D4
D3
D2
D1
D0
In normal operation, the two MSBs of the I
set to 11 by an internal ROM. However, in full power-down
mode (power down by setting Bit D7 = 1), this ROM is switched
off and the slave address MSBs become 00. Therefore, to exit the
full-power-down state, it is necessary to write to the AD7294
using this modified slave address.
After writing 0 to power down Bit D7, the slave address MSBs
return to their original 11 value.
DATA
0x0E, 0x0F (V
The DATA
read/write registers (see Table 29 and Table 30). General alert is
flagged by the MSB, D15. D14 to D12 are not used in the register
and are set to 0s. The remaining 12 bits set the high and low limits
for the relevant channel. For single-ended mode, the default values
for V
tial mode on V
DATA
the part is configured in either single-ended or differential mode
and the mode is changed, the user must reprogram the limits in
the DATA
Channel 7 to Channel 9 (T
to 3FF and 400 for the DATA
they are in twos complement 11-bit format.
IN
LOW
0 to V
HIGH
HIGH
are 7FF and 800, twos complement format. Note that if
HIGH
/DATA
Function
Power down the full chip
Reserved
Power down the ADC reference buffer (to allow
external reference, 1 at power-up)
Power down the DAC reference buffer (to allow
external reference, 1 at power-up)
Power down the temperature sensor
Power down I
Power down I
DAC outputs set to high impedance (set
automatically if die temperature >150°C)
IN
and DATA
3, are 000 and FFF in binary format. For differen-
IN
and DATA
IN
0 to V
1); 0x11, 0x12 (V
LOW
IN
REGISTERS: 0x0B, 0x0C (V
3, the default values for DATA
LOW
LOW
SENSE
SENSE
SENSE
registers.
HIGH
registers for a channel are 16-bit,
1
2
1, T
and DATA
SENSE
IN
2, and T
2); 0x14, 0x15 (V
2
C slave address are
LOW
SENSE
limits because
INT) default
HIGH
IN
0);
and
IN
Rev. F | Page 32 of 48
3)
Table 28. Default Values for DATA
Registers
ADC
Channel
V
V
V
V
I
I
T
T
T
Table 29. AD7294 DATA
MSB
D15
Alert_Flag
Table 30. AD7294 DATA
MSB
D7
B7
HYSTERESIS REGISTERS: 0x0D (V
0x13 (V
Each hysteresis register is a 16-bit read/write register wherein
only the 12 LSBs of the register are used; the MSB signals the
alert event. If FFF is written to the hysteresis register, the hyste-
resis register enters the minimum/maximum mode, see the
Alerts and Limits Theory section for further details.
Table 31. Hysteresis Register (First Read/Write)
MSB
D15
Alert_Flag
Table 32. Hysteresis Register (Second Read/Write)
MSB
D7
B7
SENSE
SENSE
IN
IN
IN
IN
SENSE
SENSE
SENSE
0
1
2
3
1
2
1
2
INT
D6
B6
D6
B6
IN
2), 0x16 (V
DATA
000
000
000
000
N/A
N/A
N/A
N/A
N/A
D14
0
D14
0
D5
B5
D5
B5
LOW
Single-Ended
D13
0
D13
0
DATA
FFF
FFF
FFF
FFF
N/A
N/A
N/A
N/A
N/A
IN
D4
B4
D4
B4
HIGH
HIGH
3)
D12
0
D12
0
/
HIGH
/
LOW
LOW
D3
B3
D3
B3
Register (Second Read/Write)
Register (First Read/Write)
D11
B11
D11
B11
HIGH
and DATA
DATA
800
800
800
800
800
800
400
400
400
D2
B2
IN
D2
B2
0), 0x10 (V
D10
B10
D10
B10
LOW
Differential
D1
B1
D1
B1
D9
B9
D9
B9
LOW
IN
DATA
7FF
7FF
7FF
7FF
7FF
7FF
3FF
3FF
3FF
LSB
D0
B0
1),
LSB
D0
B0
LSB
D8
B8
LSB
D8
B8
HIGH