AD7294BSUZ Analog Devices Inc, AD7294BSUZ Datasheet - Page 30

• Manufacturer Part Number: AD7294BSUZ
• Description: IC ADC 12BIT W/DAC/TEMP 64TQFP
• Manufacturer: Analog Devices Inc
• Type: ADC, DACr

Specifications of AD7294BSUZ

• Resolution (bits): 12 b
• Data Interface: Serial
• Sampling Rate (per Second): 22.22k
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -55°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Sampling Rate: 22.22kSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Digital: 4.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7294
DAC
Writing to these register addresses sets the DAC
and DAC
the write result register are the data bits sent to DAC
to Bit D12 are ignored.
Table 17. DAC Register (First Write)
MSB
D15
X
1
Table 18. DAC Register (Second Write)
MSB
D7
B7
Table 19. Alert Status Register A
Alert Bit
Function
Table 20. Alert Status Register B
Alert Bit
Function
Table 21. Alert Status Register C
Alert Bit
Function
Table 22. Channel Sequence Register
Channel Bit
Function
X is don’t care.
A
, DAC
D
D6
B6
output voltage codes, respectively. Bits[D11:D0] in
B
D14
X
, DAC
D7
V
high alert
D7
Reserved
D7
Reserved
D7
Open-diode
flag
IN
3
D5
B5
C
, DAC
D13
X
D4
B4
D
, REGISTERS (0x01 TO 0x04)
D12
X
D6
V
low alert
D6
Reserved
D6
Overtemp
alert
D6
Reserved
IN
3
D3
B3
D11
B11
1
D2
B2
D5
V
high alert
D10
B10
D5
I
overrange
D5
T
high alert
D5
I
IN
SENSE
A
SENSE
SENSE
2
, DAC
D1
B1
2
2
INT
A
. Bit D15
D9
B9
B
, DAC
LSB
D0
B0
LSB
D8
B8
Rev. F | Page 30 of 48
D4
V
low alert
C
IN
D4
I
overrange
D4
T
low alert
D4
I
,
SENSE
SENSE
2
SENSE
1
1
INT
ALERT STATUS REGISTER A (0x05), REGISTER B
(0x06), AND REGISTER C (0x07)
The alert status registers (A, B, and C) are 8-bit read/write
registers that provide information on an alert event. If a
conversion results in activating the ALERT/BUSY pin or the
alert_flag bit in the result register or T
status register can be read to gain further information. To clear
the full content of any one of the alert registers, write a code of
FF (all ones) to the relevant registers. Alternatively, the user can
write to the respective alert bit in the selected alert register to
clear the alert associated with that bit. The entire contents of all
the alert status registers can be cleared by writing a 1 to Bit D1
and Bit D2 in the configuration register, as shown in Table 24.
However, this operation then enables the ALERT/BUSY pin for
subsequent conversions. See the Alerts and Limits Theory
section for more details.
CHANNEL SEQUENCE REGISTER (0x08)
The channel sequence register is an 8-bit read/write register that
allows the user to sequence the ADC conversions to be per-
formed in autocycle mode. Table 22 shows the content of the
channel sequence register. See the Modes of Operation section
for more information.
D3
V
high alert
IN
D3
I
high alert
D3
T
high alert
D3
V
SENSE
SENSE
1
IN
3
2
2
D2
V
low alert
IN
D2
I
low alert
D2
T
low alert
D2
V
SENSE
SENSE
1
IN
2
2
2
D1
V
high alert
D1
V
D1
I
high alert
D1
T
high alert
SENSE
IN
SENSE
IN
0
SENSE
1
1
1
registers, the alert
D0
V
D0
I
low alert
D0
T
low alert
D0
V
low alert
SENSE
SENSE
IN
IN
0
0
1
1