ADC12451CIJ National Semiconductor, ADC12451CIJ Datasheet - Page 6

IC ADC 12BIT DYNAM TEST 24CDIP

ADC12451CIJ

Manufacturer Part Number
ADC12451CIJ
Description
IC ADC 12BIT DYNAM TEST 24CDIP
Manufacturer
National Semiconductor
Datasheet

Specifications of ADC12451CIJ

Number Of Bits
12
Sampling Rate (per Second)
83k
Data Interface
Parallel
Number Of Converters
2
Power Dissipation (max)
113mW
Voltage Supply Source
Analog and Digital, Dual ±
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
24-CDIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*ADC12451CIJ

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Electrical Characteristics
Note 7 A diode exists between AV
To guarantee accuracy it is required that the AV
Note 8 Accuracy is guaranteed at f
Note 9 Typicals are at T
Note 10 Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level)
Note 11 Positive linearity error is defined as the deviation of the analog value expressed in LSBs from the straight line that passes through positive full scale and
zero For negative linearity error the straight line passes through negative full scale and zero (See Figures 1b and 1c )
Note 12 The ADC12451’s self-calibration technique ensures linearity full scale and offset errors as specified but noise inherent in the self-calibration process will
result in a repeatability uncertainty of
Note 13 If T
Note 14 After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes
Note 15 When using the WR control to start a conversion if the clock is asynchronous to the rising edge of WR an uncertainty of one clock period will exist in the
end of the interval of t
clock is synchronous to the rising edge of WR then t
Note 16 The CAL line must be high before a conversion is started
Note 17 The specifications for these parameters are valid after an Auto-Cal cycle has been completed
Note 18 The ADC12451 reference ladder is composed solely of capacitors
Note 19 A military RETS electrical test specification is available on request At time of printing the ADC12451CMJ 883 RETS specification complies fully with the
boldface limits in this column
A
changes then an Auto-Zero or Auto-Cal cycle will have to be re-started see the typical performance characteristic curves
A
therefore making t
J
e
25 C and represent most likely parametric norm
CLK
CC
g
and DV
e
0 20 LSB
3 5 MHz At higher or lower clock frequencies accuracy may degrade see the typical performance characteristic curves
A
end a minimum 6 clock periods or a maximum 7 clock periods after the rising edge of WR If the falling edge of the
CC
CC
as shown below
A
and DV
will end exactly 6 5 clock periods after the rising edge of WR This does not occur when S H control is used
(Continued)
FIGURE 1a Transfer Characteristic
CC
be connected together to a power supply with separate bypass filters at each V
6
TL H 11025– 5
CC
pin
TL H 11025 – 6

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