ADC12451CIJ National Semiconductor, ADC12451CIJ Datasheet - Page 12

• Manufacturer Part Number: ADC12451CIJ
• Description: IC ADC 12BIT DYNAM TEST 24CDIP
• Manufacturer: National Semiconductor

Specifications of ADC12451CIJ

• Number Of Bits: 12
• Sampling Rate (per Second): 83k
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 113mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 24-CDIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *ADC12451CIJ

1 0 Pin Descriptions
DV
AV
V
DGND (12)
AGND (3)
V
V
CS (10)
RD (23)
WR (7)
S H (11)
CLKIN (8)
CAL (9)
AZ (6)
b
REF
IN
CC
CC
(5)
(1)
(2)
(24)
(4)
The digital and analog positive power supply
pins The digital and analog power supply
voltage range of the ADC12451 is
that the AV
gether to the same power supply with sepa-
rate bypass capacitors (10
parallel with a 0 1
pin
The analog negative supply voltage pin V
has a range of
bypass capacitors of 10 F tantalum in paral-
lel with a 0 1 F ceramic
The digital and analog ground pins AGND
and DGND must be connected together ex-
ternally to guarantee accuracy
The reference input voltage pin To maintain
accuracy the voltage at this pin should not
exceed the AV
50 mV or go below
The analog input voltage pin To guarantee
accuracy the voltage at this pin should not
exceed V
V
The Chip Select control input This input is
active low and enables the WR RD and S H
functions
The Read control input With both CS and RD
low the TRI-STATE output buffers are en-
abled and the INT output is reset high
The Write control input The conversion is
started on the rising edge of the WR pulse
when CS is low When this control line is
used the end of the analog input voltage ac-
quisition window is internally controlled by the
ADC12451
The sample and hold control input This con-
trol input can also be used to start a conver-
sion With CS low the falling edge of S H
starts the analog input acquisition window
The rising edge of S H ends the acquisition
window and starts a conversion
The external clock input pin The typical clock
frequency range is 500 kHz to 6 0 MHz
The Auto-Calibration control input When
CAL is low the ADC12451 is reset and a cali-
bration cycle is initiated During the calibra-
tion cycle the values of the comparator offset
voltage and the mismatch errors in the ca-
pacitor reference ladder are determined and
stored in RAM These values are used to cor-
rect the errors during a normal cycle of A D
conversion
The Auto-Zero control input With the AZ pin
held low during a conversion the ADC12451
goes into an auto-zero cycle before the actu-
al A D conversion is started This Auto-Zero
cycle corrects for the comparator offset volt-
age The total conversion time (t
creased by 26 clock periods when Auto-Zero
is used
a
b
5 5V To guarantee accuracy it is required
by more than 50 mV
CC
CC
by more than 50 mV or go below
and DV
b
CC
4 5V to
or DV
a
F ceramic) at each V
3 5 V
CC
CC
b
be connected to-
DC
5 5V and needs
by more than
F tantalum in
a
C
) is in-
4 5V to
CC
b
12
EOC (22)
INT (21)
DB0 DB8 - The TRI-STATE output pins Twelve bit plus
DB7 DB12
(13– 20)
2 0 Functional Description
The ADC12451 is a 12-bit plus sign A D converter with the
capability of doing Auto-Zero or Auto-Calibration routines to
minimize zero full-scale and linearity errors It is a succes-
sive-approximation A D converter consisting of a DAC
comparator and a successive-approximation register (SAR)
Auto-Zero is an internal calibration sequence that corrects
for the A D’s zero error caused by the comparator’s offset
voltage Auto-Cal is a calibration cycle that not only corrects
zero error but also corrects for full-scale and linearity errors
caused by DAC inaccuracies Auto-Cal minimizes the errors
of the ADC12451 without the need of trimming during its
fabrication An Auto-Cal cycle can restore the accuracy of
the ADC12451 at any time which ensures accuracy over
temperature and time
2 1 DIGITAL INTERFACE
On power up a calibration sequence should be initiated by
pulsing CAL low with CS and S H high To acknowledge the
CAL signal EOC goes low after the falling edge of CAL and
remains low during the calibration cycle of 1399 clock peri-
ods During the calibration sequence first the comparator’s
offset is determined then the capacitive DAC’s mismatch
error is found Correction factors for these errors are then
stored in internal RAM
A conversion is initiated by taking CS and WR low If AZ is
low an Auto-Zero cycle which takes approximately 26 clock
periods is inserted before the analog input is sampled and
the actual conversion is started AZ must remain low during
the complete conversion sequence After Auto-Zero the ac-
quisition opens and the analog input is sampled for appprox-
imately 7 clock periods If AZ is high the Auto-Zero cycle is
not inserted after the rising edge of WR In this case the
acquisition window opens when the ADC12451 completes a
conversion signaled by the rising edge of EOC At the end
of the acquisition window EOC goes low signaling that the
analog input is no longer being sampled and that the A D
successive approximation conversion has started
The End-of-Conversion control output This
output is low during a conversion or a calibra-
tion cycle
The Interrupt control output This output goes
low when a conversion has been completed
and indicates that the conversion result is
available in the output latches Reading the re-
sult or starting a conversion or calibration cy-
cle will reset this output high
sign output data access is accomplished using
two successive RDs of one byte each high
byte first (DB8– DB12) The data format used
is two’s complement sign bit extended with
DB12 the sign bit DB11 the MSB and DB0 the
LSB