ADC12451CIJ National Semiconductor, ADC12451CIJ Datasheet - Page 5

• Manufacturer Part Number: ADC12451CIJ
• Description: IC ADC 12BIT DYNAM TEST 24CDIP
• Manufacturer: National Semiconductor

Specifications of ADC12451CIJ

• Number Of Bits: 12
• Sampling Rate (per Second): 83k
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 113mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 24-CDIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *ADC12451CIJ

t
t
t
t
t
t
t
t
t
t
t
Symbol
A
IA
ZA
D(EOC)L
CAL
W(CAL)L
W(WR)L
ACC
0H
PD(INT)
RR
AC Electrical Characteristics
The following specifications apply for DV
Boldface limits apply for T
Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is
functional but do not guarantee specific performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed
specifications apply only for the test conditions listed Some performance characteristics may degrade when the device is not operated under the listed test
conditions
Note 2 All voltages are measured with respect to AGND and DGND unless otherwise specified
Note 3 When the input voltage (V
5 mA The 20 mA maximum package input current rating allows the voltage at any four pins with an input current limit of 5 mA to simultaneously exceed the power
supply voltages
Note 4 The power dissipation of this device under normal operation should never exceed 191 mW (Quiescent Power Dissipation
output) Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (ex when any inputs or
outputs exceed the power supply) The maximum power dissipation must be derated at elevated temperatures and is dictated by T
temperature)
is P
resistance (
Note 5 Human body model 100 pF discharged through a 1 5 k
Note 6 Two on-chip diodes are tied to the analog input as shown below Errors in the A D conversion can occur if these diodes are forward biased more than
50 mV This means that if AV
DMax
t
1H
e
(T
JA
Acquisition Time
(Note 15)
Internal Acquisition Time
(when using WR Control Only)
Auto Zero Time
Acquisition Time
Delay from Hold Command
to Falling Edge of EOC
Calibration Time
Calibration Pulse Width
minimum WR Pulse Width
maximum Access Time
(Delay from Falling Edge of
RD to Output Data Valid)
TRI-STATE Control (Delay
from Rising Edge of RD
to Hi-Z State)
maximum Delay from Falling Edge
of RD or WR to Reset of INT
Delay between Successive RD Pulses
JMax
) of the ADC12451 with CMJ and CIJ suffixes when board mounted is 51 C W
JA
(package junction to ambient thermal resistance) and T
b
T
A
)
JA
CC
Parameter
or the number given in the Absolute Maximum Ratings whichever is lower For this device T
and DV
a
IN
A
) at any pin exceeds the power supply rails (V
e
CC
T
are minimum (4 75 V
J
e
T
MIN
CC
e
to T
AV
(Continued)
MAX
DC
CC
R
f
Using WR Control
Using S H Control
f
(Note 16)
C
R
C
CLK
CLK
resistor
) and V
SOURCE
L
L
L
e a
Conditions
e
e
e
all other limits T
e
e
100 pF
100 pF
1 k
A
b
1 75 MHz
3 5 MHz
(ambient temperature) The maximum allowable power dissipation at any temperature
5 0V V
is maximum (
e
5
IN k
50
b
V
b
e b
b
A
or V
4 75 V
1399 (1 f
e
33(1 f
IN l
7(1 f
5 0V t
(Note 9)
Typical
T
DC
18 8
J
200
100
399
100
3 5
60
60
50
30
30
(AV
e
) the analog input full-scale voltage must be
CLK
CLK
r
CC
CLK
25 C (Notes 6 and 7)
TL H 11025 – 4
e
)
)
or DV
)
t
f
e
CC
33(1 f
) the current at that pin should be limited to
20 ns unless otherwise specified
1399 (1 f
JMax
(Note 10 19)
7(1 f
CLK
19 05
Limit
e
350
150
400
200
200
175
3 5
95
70
60
a
150 C and the typical thermal
)
CLK)
a
1 TTL Load on each digital
CLK
JMax
250 ns
)
(maximum junction
s g
ns(max)
ns(max)
ns(max)
ns(max)
ns(max)
4 8 V
ns(min)
ns(min)
ns(min)
(Limit)
(max)
(max)
(max)
Units
s(max)
s(max)
s(min)
DC