ADC14C080CISQ/NOPB National Semiconductor, ADC14C080CISQ/NOPB Datasheet - Page 22

• Manufacturer Part Number: ADC14C080CISQ/NOPB
• Description: ADC 14BIT 65/80MSPS 32-LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC14C080CISQ/NOPB

• Number Of Bits: 14
• Sampling Rate (per Second): 80M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 300mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC14C080CISQ

traces and enter the ground plane at a single, quiet point. All
ground connections should have a low inductance path to
ground.
7.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance, the clock source
driving the CLK input must have a sharp transition region and
be free of jitter. Isolate the ADC clock from any digital circuitry
with buffers, as with the clock tree shown in Figure 8. The
gates used in the clock tree must be capable of operating at
frequencies much higher than those used if added jitter is to
be prevented.
As mentioned in Section 6.0, it is good practice to keep the
20209817
ADC clock line as short as possible and to keep it well away
FIGURE 8. Isolating the ADC Clock from other Circuitry
from any other signals. Other signals can introduce jitter into
with a Clock Tree
the clock signal, which can lead to reduced SNR perfor-
mance, and the clock can introduce noise into other lines.
Even lines with 90° crossings have capacitive coupling, so try
to avoid even these 90° crossings of the clock line.
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