AD9254BCPZ-150 Analog Devices Inc, AD9254BCPZ-150 Datasheet - Page 23

• Manufacturer Part Number: AD9254BCPZ-150
• Description: IC ADC 14BIT 150MSPS 48-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9254BCPZ-150

• Data Interface: Serial, SPI™
• Number Of Bits: 14
• Sampling Rate (per Second): 150M
• Number Of Converters: 3
• Power Dissipation (max): 470mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Resolution (bits): 14bit
• Sampling Rate: 150MSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9254-150EBZ - BOARD EVALUATION FOR AD9254
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

MEMORY MAP REGISTER TABLE
Table 15. Memory Map Register
Addr.
(Hex)
Chip Configuration Registers
00
01
02
Device Index and Transfer Registers
FF
Global ADC Functions
08
09
Parameter Name
chip_port_config
chip_id
chip_grade
device_update
modes
clock
Bit 7
(MSB)
0
Open
Open
Open
Open
Bit 6
LSB first
0 = Off
(Default)
1 = On
Open
Open
Open
Open
Open
Bit 5
Soft
reset
0 = Off
(Default)
1 = On
PDWN
0—Full
1—
Standby
Open
Open
(AD9254 = 0x00), (default)
8-bit Chip ID Bits 7:0
Open
Rev. 0 | Page 23 of 40
Bit 4
1
Open
Open
Open
Bit 3
1
Child ID
0 = 150
MSPS
Open
Open
Open
Bit 2
Soft
reset
0 = Off
(Default)
1 = On
Open
Open
Internal power-down mode
000—normal (power-up)
001—full power-down
010—standby
011—normal (power-up)
Note: External PDWN pin
overrides this setting.
Open
Bit 1
LSB first
0 = Off
(Default)
1 = On
Open
Open
Open
Bit 0
(LSB)
0
Open
SW
transfer
Duty
cycle
stabilizer
0—
disabled
1—
enabled
Default
Value
(Hex)
0x18
Read
only
Read
only
0x00
0x00
0x01
Default Notes/
Comments
The nibbles
should be
mirrored. See
the
High Speed ADCs
via SPI
manual.
Default is unique
chip ID, different
for each device.
Child ID used to
differentiate
speed grades.
Synchronously
transfers data
from the master
shift register to
the slave.
Determines
various generic
modes of chip
operation. See
the
Dissipation and
Standby Mode
and the
Accessible
Features
sections.
See the
Duty Cycle
section and the
SPI-Accessible
Features
AD9254
Interfacing to
Power
user
Clock
SPI-
section.