AD9254BCPZ-150 Analog Devices Inc, AD9254BCPZ-150 Datasheet - Page 20

• Manufacturer Part Number: AD9254BCPZ-150
• Description: IC ADC 14BIT 150MSPS 48-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9254BCPZ-150

• Data Interface: Serial, SPI™
• Number Of Bits: 14
• Sampling Rate (per Second): 150M
• Number Of Converters: 3
• Power Dissipation (max): 470mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Resolution (bits): 14bit
• Sampling Rate: 150MSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9254-150EBZ - BOARD EVALUATION FOR AD9254
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9254
Standby Mode
When using the SPI port interface, the user can place the ADC
in power-down or standby modes. Standby mode allows the
user to keep the internal reference circuitry powered when
faster wake-up times are required (see the Memory Map section).
DIGITAL OUTPUTS
The AD9254 output drivers can be configured to interface with
1.8 V to 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fan-outs may require external buffers or latches.
The output data format can be selected for either offset binary
or twos complement by setting the SCLK/DFS pin when operat-
ing in the external pin mode (see Table 10). As detailed in the
Interfacing to High Speed ADCs via SPI user
format can be selected for either offset binary, twos complement,
or Gray code when using the SPI control.
Out-of-Range (OR) Condition
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OR is a digital output
that is updated along with the data output corresponding to the
particular sampled input voltage. Thus, OR has the same
pipeline latency as the digital data.
OR is low when the analog input voltage is within the analog
input range and high when the analog input voltage exceeds the
input range, as shown in Figure 48. OR remains high until the
analog input returns to within the input range and another
conversion is completed.
Table 12. Output Data Format
Input (V)
VIN+ – VIN–
VIN+ – VIN–
VIN+ – VIN–
VIN+ – VIN–
VIN+ – VIN–
OR DATA OUTPUTS
1
0
0
0
0
1
Figure 48. OR Relation to Input Voltage and Output Data
11
11
11
00
00
00
1111
1111
1111
0000
0000
0000
1111
1111
1111
0000
0000
0000
Condition (V)
< –VREF – 0.5 LSB
= –VREF
= 0
= +VREF – 1.0 LSB
> +VREF – 0.5 LSB
1111
1111
1110
0001
0000
0000
–FS – 1/2 LSB
OR
–FS
–FS + 1/2 LSB
manual, the data
+FS – 1/2 LSB
+FS – 1 LSB
Binary Output Mode
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1111
+FS
Rev. 0 | Page 20 of 40
By logically AND’ing the OR bit with the MSB and its complement,
overrange high or underrange low conditions can be detected.
Table 11 is a truth table for the overrange/underrange circuit in
Figure 49, which uses NAND gates.
Table 11. Overrange/Underrange Truth Table
OR
0
0
1
1
Digital Output Enable Function (OEB)
The AD9254 has three-state ability. If the OEB pin is low, the
output data drivers are enabled. If the OEB pin is high, the
output data drivers are placed in a high impedance state. This is
not intended for rapid access to the data bus. Note that OEB is
referenced to the digital supplies (DRVDD) and should not
exceed that supply voltage.
TIMING
The lowest typical conversion rate of the AD9254 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can degrade.
The AD9254 provides latched data outputs with a pipeline delay
of twelve clock cycles. Data outputs are available one propaga-
tion delay (t
The length of the output data lines and the loads placed on
them should be minimized to reduce transients within the
AD9254. These transients can degrade the dynamic performance
of the converter.
Data Clock Output (DCO)
The AD9254 also provides data clock output (DCO) intended for
capturing the data in an external register. The data outputs are valid
on the rising edge of DCO, unless the DCO clock polarity has been
changed via the SPI. See Figure 2 for a graphical timing
description.
Twos Complement Mode
10 0000 0000 0000
10 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
MSB
MSB
OR
MSB
0
1
0
1
PD
) after the rising edge of the clock signal.
Figure 49. Overrange/Underrange Logic
Analog Input Is:
Within range
Within range
Underrange
Overrange
Gray Code Mode
(SPI Accessible)
11 0000 0000 0000
11 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
10 0000 0000 0000
OVER = 1
UNDER = 1
OR
1
0
0
0
1