AD9254BCPZ-150 Analog Devices Inc, AD9254BCPZ-150 Datasheet - Page 18

• Manufacturer Part Number: AD9254BCPZ-150
• Description: IC ADC 14BIT 150MSPS 48-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9254BCPZ-150

• Data Interface: Serial, SPI™
• Number Of Bits: 14
• Sampling Rate (per Second): 150M
• Number Of Converters: 3
• Power Dissipation (max): 470mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Resolution (bits): 14bit
• Sampling Rate: 150MSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9254-150EBZ - BOARD EVALUATION FOR AD9254
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9254
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins as shown in Figure 42. The
AD9513/AD9514/AD9515
excellent jitter performance.
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 43. The
AD9511/AD9512/AD9513/AD9514/AD9515
drivers offers excellent jitter performance.
CLOCK
CLOCK
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
directly drive CLK+ from a CMOS gate, while bypassing the
CLK− pin to ground using a 0.1 μF capacitor in parallel with a
39 kΩ resistor (see Figure 44). CLK+ can be directly driven
from a CMOS gate. This input is designed to withstand input
voltages up to 3.6 V, making the selection of the drive logic
voltage very flexible. When driving CLK+ with a 1.8 V CMOS
signal, biasing the CLK− pin with a 0.1 μF capacitor in parallel
with a 39 kΩ resistor (see Figure 44) is required. The 39 kΩ
resistor is not required when driving CLK+ with a 3.3 V CMOS
signal (see Figure 45).
CLOCK
CLOCK
INPUT
INPUT
INPUT
CLOCK
INPUT
INPUT
50Ω
1
50Ω
1
50Ω RESISTORS ARE OPTIONAL.
50Ω RESISTORS ARE OPTIONAL.
1
1
Figure 41. Transformer Coupled Differential Clock
50Ω
0.1µF
Figure 42. Differential PECL Sample Clock
Figure 43. Differential LVDS Sample Clock
50Ω
0.1µF
0.1µF
0.1µF
0.1µF
50Ω
100Ω
1
1
ADT1–1WT, 1:1Z
LVDS DRIVER
CLK
CLK
MINI-CIRCUITS
CLK
PECL DRIVER
CLK
AD951x
AD951x
XFMR
0.1µF
family of clock drivers offers
240Ω
0.1µF
0.1µF
AD9510/AD9511/AD9512/
SCHOTTKY
HMS2812
DIODES:
240Ω
100Ω
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
family of clock
CLK+
CLK–
AD9254
CLK+
CLK–
CLK+
CLK–
AD9510/
AD9254
AD9254
ADC
ADC
ADC
Rev. 0 | Page 18 of 40
CLOCK
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9254 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling, or falling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9254. Noise and distortion performance are nearly flat
for a wide range of duty cycles when the DCS is on, as shown in
Figure 28.
Jitter in the rising edge of the input is still of paramount concern
and is not reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz nominally. The loop has a time constant associated
with it that needs to be considered in applications where the
clock rate can change dynamically. This requires a wait time
of 1.5 μs to 5 μs after a dynamic clock frequency increase (or
decrease) before the DCS loop is relocked to the input signal.
During the time period the loop is not locked, the DCS loop is
bypassed, and the internal device timing is dependent on the
duty cycle of the input clock signal. In such an application, it
may be appropriate to disable the duty cycle stabilizer. In all
other applications, enabling the DCS circuit is recommended
to maximize ac performance.
CLOCK
INPUT
INPUT
1
50Ω RESISTOR IS OPTIONAL.
50Ω
50Ω
1
50Ω RESISTOR IS OPTIONAL.
Figure 44. Single-Ended 1.8 V CMOS Sample Clock
Figure 45. Single-Ended 3.3 V CMOS Sample Clock
0.1µF
0.1µF
1
1
VCC
VCC
1kΩ
1kΩ
1kΩ
1kΩ
CMOS DRIVER
CMOS DRIVER
AD951x
AD951x
0.1µF
OPTIONAL
OPTIONAL
100Ω
100Ω
39kΩ
0.1µF
0.1µF
0.1µF
CLK+
CLK–
CLK+
CLK–
AD9254
AD9254
ADC
ADC