AD7982BRMZ Analog Devices Inc, AD7982BRMZ Datasheet - Page 16

• Manufacturer Part Number: AD7982BRMZ
• Description: IC ADC 18BIT 1MSPS PULSAR 10MSOP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7982BRMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Design Resources: Converting a Single-Ended Signal with AD7982 Differential PulSAR ADC (CN0032) Precision Single-Supply Differential ADC Driver for Industrial-Level Signals (CN0180)
• Number Of Bits: 18
• Sampling Rate (per Second): 1M
• Number Of Converters: 1
• Power Dissipation (max): 8.6mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP (0.118", 3.00mm Width)
• Resolution (bits): 18bit
• Sampling Rate: 1MSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 2.375V To 2.625V
• Supply Current: 350nA
• Package: 10MSOP
• Resolution: 18 Bit
• Architecture: SAR
• Number Of Analog Inputs: 1
• Digital Interface Type: Serial (3-Wire, 4-Wire, SPI, QSPI, Microwire)
• Input Type: Voltage
• Signal To Noise Ratio: 98(Typ) dB
• Polarity Of Input Voltage: Bipolar
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7982
DIGITAL INTERFACE
Although the AD7982 has a reduced number of pins, it offers
flexibility in its serial interface modes.
When in CS mode, the AD7982 is compatible with SPI, QSPI,
digital hosts, and DSPs. In this mode, the AD7982 can use
either a 3-wire or 4-wire interface. A 3-wire interface using the
CNV, SCK, and SDO signals minimizes wiring connections
useful, for instance, in isolated applications. A 4-wire interface
using the SDI, CNV, SCK, and SDO signals allows CNV, which
initiates the conversions, to be independent of the readback
timing (SDI). This is useful in low jitter sampling or
simultaneous sampling applications.
When in chain mode, the AD7982 provides a daisy-chain feature
using the SDI input for cascading multiple ADCs on a single
data line similar to a shift register.
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The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high, and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is always selected.
In either mode, the AD7982 offers the option of forcing a start
bit in front of the data bits. This start bit can be used as a busy
signal indicator to interrupt the digital host and trigger the data
reading. Otherwise, without a busy indicator, the user must timeout
the maximum conversion time prior to readback.
The busy indicator feature is enabled
•
•
In the CS mode if CNV or SDI is low when the ADC
conversion ends (see Figure 32 and Figure 36).
In the chain mode if SCK is high during the CNV rising
edge (see Figure 40).