AD1674KNZ Analog Devices Inc, AD1674KNZ Datasheet - Page 7

• Manufacturer Part Number: AD1674KNZ
• Description: IC ADC 12BIT 100KSPS 28-DIP
• Manufacturer: Analog Devices Inc

Specifications of AD1674KNZ

• Data Interface: Parallel
• Number Of Bits: 12
• Sampling Rate (per Second): 100k
• Number Of Converters: 1
• Power Dissipation (max): 825mW
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 28-DIP (0.600", 15.24mm)
• Resolution (bits): 12bit
• Sampling Rate: 100kSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Digital: 4.5V To 5.5V
• Supply Current: 14mA
• Digital Ic Case Style: DIP
• Number Of Elements: 1
• Resolution: 12Bit
• Architecture: SAR
• Sample Rate: 100KSPS
• Input Polarity: Unipolar/Bipolar
• Input Type: Voltage
• Rated Input Volt: 10/20/±5/±10V
• Differential Input: No
• Power Supply Requirement: Dual
• Single Supply Voltage (typ): Not RequiredV
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (typ): ±12/±15V
• Dual Supply Voltage (min): ±11.4V
• Dual Supply Voltage (max): ±16.5V
• Power Dissipation: 575mW
• Integral Nonlinearity Error: ±0.5LSB
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 28
• Package Type: PDIP W
• Input Signal Type: Single-Ended
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

DSCC FORM 2234
APR 97
Converter start timing section (see figure 4)
Conversion time
STS delay from CE
CE pulse width
R/ C to CE setup
R/ C low during CE high
A
A
Read timing full control mode section (see figure 5)
Access time
Data valid after CE low
Output float delay
CS to CE setup
CS low during CE high
See footnotes at end of table.
O
O
to CE setup
valid during CE high
DEFENSE SUPPLY CENTER COLUMBUS
Test
MICROCIRCUIT DRAWING
COLUMBUS, OHIO 43216-5000
STANDARD
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
C
DSC
HEC
SSC
HSC
SRC
HRC
SAC
HAC
DD
HD
HL
TABLE I. Electrical performance characteristics – Continued.
8-bit cycle
12-bits cycle
See figures 8 and 9
See figures 8 and 9
See figures 8 and 9
V
unless otherwise specified
CC
-55 C
= +15 V, V
V
Conditions 1/
LOGIC
T
A
= +5 V
EE
+125 C
= -15 V,
SIZE
A
subgroups
Group A
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
9,10,11
10,11
10,11
9
9
REVISION LEVEL
Device
type
01
01
01
01
01
01
01
01
01
01
01
01
A
Min
50
50
50
50
50
50
25
15
0
Limits
Max
SHEET
200
225
150
150
10
8
5962-93164
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
s
Unit