AD7710ANZ Analog Devices Inc, AD7710ANZ Datasheet - Page 22

• Manufacturer Part Number: AD7710ANZ
• Description: IC ADC SIGNAL CONDITIONING 24DIP
• Manufacturer: Analog Devices Inc

Specifications of AD7710ANZ

• Data Interface: Serial
• Number Of Bits: 24
• Sampling Rate (per Second): 1.03k
• Number Of Converters: 1
• Power Dissipation (max): 45mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (0.300", 7.62mm)
• Resolution (bits): 24bit
• Sampling Rate: 1.02kSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Digital: 4.75V To 5.25V
• Supply Current: 4.5mA
• Digital Ic Case Style: DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7710
Figures 12a and 12b show timing diagrams for reading from the
AD7710 in external clocking mode. In Figure 12a, all the data is
read from the AD7710 in one read operation. In Figure 12b, the
data is read from the AD7710 over a number of read operations.
Both read operations show a read from the AD7710’s output
data register. A read from the control register or calibration
registers is similar, but, in these cases, the DRDY line is not
related to the read function. Depending on the output update
rate, it can go low at any stage in the control/calibration register
read cycle without affecting the read, and its status should be
ignored. A read operation from either the control or calibration
registers must always read 24 bits of data.
Figure 12a shows a read operation from the AD7710 where
RFS remains low for the duration of the data-word transmis-
sion. With DRDY low, the RFS input is brought low. The input
SCLK signal should be low between read and write operations.
RFS going low places the MSB of the word to be read on the
serial data line. All subsequent data bits are clocked out on a
high to low transition of the serial clock and are valid prior to
the following rising edge of this clock. The penultimate falling
edge of SCLK clocks out the LSB and the final falling edge
Figure 12b. External Clocking Mode, Output Data Read Operation ( RFS Returns High during Read Operation)
SDATA (O)
SDATA (O)
DRDY (O)
DRDY (O)
SCLK (I)
SCLK (I)
RFS (I)
RFS (I)
A0 (I)
A0 (I)
Figure 12a. External Clocking Mode, Output Data Read Operation
t
20
t
t
20
22
t
22
t
t
24
24
t
MSB
26
MSB
t
25
t
25
–22–
t
27
resets the DRDY line high. This rising edge of DRDY turns off
the serial data output.
Figure 12b shows a timing diagram for a read operation where
RFS returns high during the transmission of the word and
returns low again to access the rest of the data-word. Timing
parameters and functions are very similar to that outlined for
Figure 12a, but Figure 12b has a number of additional times to
show timing relationships when RFS returns high in the middle
of transferring a word.
RFS should return high during a low time of SCLK. On the
rising edge of RFS, the SDATA output is turned off. DRDY
remains low and will remain low until all bits of the data-word
are read from the AD7710, regardless of the number of times
RFS changes state during the read operation. Depending on the
time between the falling edge of SCLK and the rising edge of
RFS, the next bit (BIT N+1) may appear on the data bus before
RFS goes high. When RFS returns low again, it activates the
SDATA output. When the entire word is transmitted, the
DRDY line will go high, turning off the SDATA output as
shown in Figure 12a.
BIT N
t
26
THREE-STATE
t
27
t
30
t
31
LSB
t
24
t
29
t
21
BIT N+1
t
THREE-STATE
t
28
23
t
25
REV. G