AD7715ANZ-3 Analog Devices Inc, AD7715ANZ-3 Datasheet - Page 4

• Manufacturer Part Number: AD7715ANZ-3
• Description: IC ADC 16BIT SIGMA-DELTA 16DIP
• Manufacturer: Analog Devices Inc

Specifications of AD7715ANZ-3

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 500
• Number Of Converters: 1
• Power Dissipation (max): 9.5mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Resolution (bits): 16bit
• Input Channel Type: Differential
• Supply Voltage Range - Analogue: 3V To 3.6V
• Supply Voltage Range - Digital: 3V To 5.25V
• Supply Current: 600µA
• No. Of: RoHS Compliant
• Sampling Rate: 19.2kSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7715-3EBZ - BOARD EVALUATION FOR AD7715
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7715–SPECIFICATIONS
(AD7715-5); REF IN(–) = AGND; MCLK IN = 1 MHz to 2.4576 MHz unless otherwise noted. All specifications T
Pa
SYSTEM CALIBRATION
POWER REQUIREMENTS
NOTES
10
11
12
13
14
15
16
17
18
19
20
Specifications subject to change without notice.
1
2
3
4
5
6
7
8
9
Temperature Range as follows: A Version, –40 C to +85 C.
A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables V to XII. This applies after calibration at the
temperature of interest.
Recalibration at any temperature will remove these drift errors.
Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges.
Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.
Gain Error does not include Zero-Scale Errors. It is calculated as Full-Scale Error–Unipolar Offset Error for unipolar ranges and Full-Scale Error–Bipolar Zero Error
for bipolar ranges.
Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero scale calibrations only were performed.
These numbers are guaranteed by design and/or characterization.
This common-mode voltage range is allowed provided that the input voltage on AIN(+) or AIN(–) does not go more positive than A V
tive than AGND – 30 mV.
The analog input voltage range on AIN(+) is given here with respect to the voltage on AIN(–). The absolute voltage on the analog inputs should not go more posi-
tive than AV
V
These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.
Sample tested at +25 C to ensure compliance.
After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will
output all 0s.
These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV
30 mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
Assumes CLK Bit of Setup Register is set to correct status corresponding to the master clock frequency.
When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DV
the crystal or resonator type (see Clocking and Oscillator Circuit section).
Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120 dB
with filter notches of 20 Hz or 60 Hz.
PSRR depends on gain. Gain of 1: 85 dB typ; Gain of 2: 90 dB typ; Gains of 32 and 128: 95 dB typ.
If the external master clock continues to run in standby mode, the standby current increases to 50 A typical. When using a crystal or ceramic resonator across the
MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or
resonator type (see Standby Mode section).
Positive Full-Scale Calibration Limit
Negative Full-Scale Calibration Limit
Offset Calibration Limit
Input Span
Power Supply Voltages
Power Supply Currents
Power Supply Rejection
Normal-Mode Power Dissipation
Normal-Mode Power Dissipation
Standby (Power-Down) Current
Standby (Power-Down) Current
REF
rameter
AV
AV
DV
AV
DV
= REF IN(+) – REF IN(–).
DD
DD
DD
DD
DD
Voltage (AD7715-3)
Voltage (AD7715-5)
Current
Current
Voltage
DD
15
+ 30 mV or go more negative than AGND – 30 mV.
17
15
18
20
20
17
17
14
14
A Version
(1.05
–(1.05
–(1.05
0.8
(2.1
+3 to +3.6
+4.75 to +5.25
+3 to +5.25
0.27
0.6
0.5
1.1
0.18
0.4
0.5
0.8
See Note 19
1.5
2.65
3.3
5.3
3.25
5
6.5
9.5
20
10
A
V
V
REF
V
REF
V
V
REF
/GAIN
REF
REF
)/GAIN
)/GAIN
)/GAIN
)/GAIN
(AV
DD
= +3 V to +5 V, DV
mA max
mA max
mA max
mA max
mA max
mA max
mA max
mA max
mW max
mW max
mW max
mW max
mW max
mW max
Unit
V max
V max
V max
V min
V max
V
V
V
dB typ
mW max
mW max
A max
A max
–4–
Conditions/Comments
GAIN Is the Selected PGA Gain (1, 2, 32 or 128)
GAIN Is the Selected PGA Gain (1, 2, 32 or 128)
GAIN Is the Selected PGA Gain (1, 2, 32 or 128)
GAIN Is the Selected PGA Gain (1, 2, 32 or 128)
GAIN Is the Selected PGA Gain (1, 2, 32 or 128)
For Specified Performance
For Specified Performance
For Specified Performance
AV
Gain = 1 or 2 (f
Typically 0.2 mA. BUF Bit of Setup Register = 0
Typically 0.4 mA. BUF Bit of Setup Register = 1
AV
Typically 0.3 mA. BUF Bit of Setup Register = 0
Typically 0.8 mA. BUF Bit of Setup Register = 1
Digital I/Ps = 0 V or DV
Typically 0.15 mA. DV
Typically 0.3 mA. DV
Typically 0.4 mA. DV
Typically 0.6 mA. DV
AV
BUF Bit = 0. All Gains 1 MHz Clock
BUF Bit = 1. All Gains 1 MHz Clock
BUF Bit = 0. Gain = 32 or 128 @ f
BUF Bit = 1. Gain = 32 or 128 @ f
AV
BUF Bit = 0. All Gains 1 MHz Clock
BUF Bit = 1. All Gains 1 MHz Clock
BUF Bit = 0. Gain = 32 or 128 @ f
BUF Bit = 1. Gain = 32 or 128 @ f
External MCLK IN = 0 V or DV
External MCLK IN = 0 V or DV
DD
DD
DD
DD
DD
= DV
= DV
= 3.3 V or 5 V. Gain = 32 or 128 (f
= 3.3 V or 5 V. Gain = 1 to 128 (f
= +3 V to +5 V, REF IN(+) = +1.25 V (AD7715-3) or +2.5 V
DD
DD
= +3.3 V. Digital I/Ps = 0 V or DV
= +5 V. Digital I/Ps = 0 V or DV
CLK IN
DD
DD
current and power dissipation will vary depending on
DD
DD
DD
= 2.4576 MHz)
DD
+ 30 mV or go more negative than AGND –
DD
= 5 V. f
= 3.3 V. f
= 5 V. f
= 3.3 V. f
. External MCLK IN
MIN
CLK IN
CLK IN
DD
DD
CLK IN
CLK IN
CLK IN
CLK IN
CLK IN
. Typically 10 A. V
. Typically 5 A. V
to T
CLK IN
= 1 MHz
= 2.4576 MHz
MAX
CLK IN
CLK IN
= 2.4576 MHz
DD
= 2.4576 MHz
= 2.4576 MHz
= 2.4576 MHz
= 2.4576 MHz
= 1 MHz
unless otherwise noted.)
+ 30 mV or go more nega-
DD
DD
= 2.4576 MHz)
= 1 MHz) or
. External MCLK IN
. External MCLK IN
DD
DD
= +3.3 V
= +5 V
REV. C
16