AD7366BRUZ-5 Analog Devices Inc, AD7366BRUZ-5 Datasheet - Page 9

• Manufacturer Part Number: AD7366BRUZ-5
• Description: IC ADC 12BIT DUAL 500KSPS 24-TSS
• Manufacturer: Analog Devices Inc

Specifications of AD7366BRUZ-5

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Design Resources: Driving the AD7366/7 Bipolar SAR ADC in Low-Distortion DC-Coupled Appls (CN0042)
• Number Of Bits: 12
• Sampling Rate (per Second): 500k
• Number Of Converters: 2
• Power Dissipation (max): 88.8mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 12bit
• Input Channel Type: Single Ended
• Supply Voltage Range - Analogue: 4.75V To 5.25V, ± 11.5V To ± 16.5V
• Supply Voltage Range - Digital: 2.7V To 5.25V,
• Sampling Rate: 1MSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7366CBZ - BOARD EVALUATION FOR AD7366
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
1, 23
2
3
4, 5
6
7, 17
8
9, 16
10
11, 12
13, 14
15
Mnemonic
D
V
DV
RANGE1,
RANGE0
ADDR
AGND
AV
D
V
V
V
V
DRIVE
SS
A1
B2
DD
OUT
CAP
CC
CC
, V
, V
A, D
A, D
B1
A2
CAP
OUT
B
B
Description
Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on
the falling edge of the SCLK input and 12 SCLK cycles are required to access the data from the AD7366-5 while
14 SCLK cycle are required for the AD7367-5. The data simultaneously appears on both pins from the simultaneous
conversions of both ADCs. The data stream consists of the 12 bits of conversion data for the AD7366-5 and 14 bits
for the AD7367-5 and is provided MSB first. If CS is held low for a further 12 SCLK cycles for the AD7366-5 or 14 SCLK
cycles for the AD7367-5, on either D
allows data from a simultaneous conversion on both ADCs to be gathered in serial format on either D
D
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
This pin should be decoupled to DGND. The voltage range on this pin is 2.7 V to 5.25 V and may be different than
the voltage at AV
Digital Supply Voltage, 4.75 V to 5.25 V. The DV
For best performance, it is recommended that the DV
voltage difference between them never exceeds 0.3 V, even on a transient basis. This supply should be decoupled
to DGND. Place 10 μF and 100 nF decoupling capacitors on the DV
Analog Input Range Selection, Logic Inputs. The polarity on these pins determines the input range of the analog
input channels. See the Analog Inputs section and Table 8 for details.
Multiplexer Select, Logic Input. This input is used to select the pair of channels to be simultaneously converted,
either Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and ADC B. The logic state on this pin is
latched on the rising edge of BUSY to set up the multiplexer for the next conversion.
Analog Ground. Ground reference point for all analog circuitry on the AD7366-5/AD7367-5. All analog input
signals and any external reference signal should be referred to this AGND voltage. Both AGND pins should
connect to the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC cores. The AV
should ideally be at the same potential. For best performance, it is recommended that the DV
shorted together to ensure that the voltage difference between them never exceeds 0.3 V even on a transient
basis. This supply should be decoupled to AGND. Place 10 μF and 100 nF decoupling capacitors on the AV
Decoupling Capacitor Pins. Decoupling capacitors are connected to these pins to decouple the reference buffer
for each respective ADC. For best performance, it is recommended to use a 680 nF decoupling capacitor on these
pins. Provided the output is buffered, the on-chip reference can be taken from these pins and applied externally
to the rest of a system.
Negative Power Supply Voltage. This is the negative supply voltage for the high voltage analog input structure
of the AD7366-5/AD7367-5. The supply must be less than or equal to −5 V (see Table 7 for further details).
Place 10 μF and 100 nF decoupling capacitors on the V
Analog Inputs of ADC A. These are both single-ended analog inputs. The analog input range on these channels is
determined by the RANGE0 and RANGE1 pins.
Analog Inputs of ADC B. These are both single-ended analog inputs. The analog input range on these channels is
determined by the RANGE0 and RANGE1 pins.
Positive Power Supply Voltage. This is the positive supply voltage for the high voltage analog input structure
of the AD7366-5/AD7367-5. The supply must be greater than or equal to 5 V (see Table 7 for further details).
Place 10 μF and 100 nF decoupling capacitors on the V
OUT
B using only one serial port. See the
CC
and DV
RANGE1
RANGE0
CC
D
V
D
, but should never exceed either by more than 0.3 V.
ADDR
AGND
DV
OUT
DRIVE
AV
CAP
V
V
V
CC
CC
SS
A1
A2
A
A
Figure 2. Pin Configuration
10
11
12
1
2
3
4
5
6
7
8
9
Rev. A | Page 9 of 28
OUT
AD7366-5/
(Not to Scale)
AD7367-5
TOP VIEW
A or D
Serial Interface
OUT
CC
B, the data from the other ADC follows on that D
and AV
24
23
22
21
20
19
18
17
16
15
14
13
DGND
D
BUSY
CNVST
SCLK
CS
REFSEL
AGND
D
V
V
V
DD
B1
B2
OUT
CAP
CC
SS
DD
CC
and AV
B
B
section for more information.
pin.
pin.
voltages should ideally be at the same potential.
CC
pins be shorted together, to ensure that the
CC
pin.
AD7366-5/AD7367-5
CC
and DV
CC
and AV
OUT
pin. This
CC
OUT
CC
voltages
A or
pins be
CC
pin.