LTC2206IUK-14#PBF Linear Technology, LTC2206IUK-14#PBF Datasheet - Page 15

• Manufacturer Part Number: LTC2206IUK-14#PBF
• Description: IC ADC 14BIT 80MSPS 48-QFN
• Manufacturer: Linear Technology

Specifications of LTC2206IUK-14#PBF

• Number Of Bits: 14
• Sampling Rate (per Second): 80M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 875mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN FUNCTIONS
OF (Pin 43): Over/Under Flow Digital Output. OF is high
when an over or under fl ow has occurred.
OE (Pin 44): Output Enable Pin. Low enables the digital
output drivers. High puts digital outputs in Hi-Z state.
MODE (Pin 45): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty
cycle stabilizer. Connecting MODE to 1/3V
binary output format and enables the clock duty cycle sta-
bilizer. Connecting MODE to 2/3V
output format and enables the clock duty cycle stabilizer.
Connecting MODE to V
format and disables the clock duty cycle stabilizer.
BLOCK DIAGRAM
SENSE
A
A
V
IN
IN
CM
+
–
GENERATOR
INPUT
S/H
DITHER
SIGNAL
BUFFER
REFERENCE
VOLTAGE
SELECT
RANGE
DD
FIRST PIPELINED
selects 2’s complement output
ADC STAGE
DD
PGA
selects 2’s complement
DD
ADC
REFERENCE
SECOND PIPELINED
selects offset
Figure 1. Functional Block Diagram
ADC STAGE
DIFFERENTIAL
ADC CLOCKS
LOW JITTER
ENC
DRIVER
CLOCK
INPUT
+
ENC
–
THIRD PIPELINED
RAND (Pin 46): Digital Output Randomization Selection
Pin. RAND low results in normal operation. RAND high
selects D1-D13 to be EXCLUSIVE-ORed with D0 (the
LSB). The output can be decoded by again applying an
XOR operation between the LSB and all other bits. This
mode of operation reduces the effects of digital output
interference.
PGA (Pin 47): Programmable Gain Amplifi er Control Pin. Low
selects a front-end gain of 1, input range of 2.25V
selects a front-end gain of 1.5, input range of 1.5V
GND (Exposed Pad, Pin 49): ADC Power Ground. The ex-
posed pad on the bottom of the package must be soldered
to ground.
ADC STAGE
SHDN
PGA RAND
LTC2207-14/LTC2206-14
CONTROL
LOGIC
MODE
FOURTH PIPELINED
ADC STAGE
DITH
OE
CORRECTION LOGIC
FIFTH PIPELINED
SHIFT REGISTER
ADC STAGE
DRIVERS
OUTPUT
AND
OGND
2207614 F01
P-P
220714614fc
•
•
•
15
P-P
. High
CLKOUT+
CLKOUT–
OF
D13
D12
D1
D0
GND
OV
V
.
DD
DD